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		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2020s2-7511_SQL_Database_for_Experimental_Metadata&amp;diff=16234</id>
		<title>Projects:2020s2-7511 SQL Database for Experimental Metadata</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2020s2-7511_SQL_Database_for_Experimental_Metadata&amp;diff=16234"/>
		<updated>2021-06-04T06:19:46Z</updated>

		<summary type="html">&lt;p&gt;A1702535: by Junwen&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:2020s2-7511 SQL Database for Experimental Metadata]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2020 s2|7511 SQL Database for Experimental Metadata]]&lt;br /&gt;
Abstract here&lt;br /&gt;
== Introduction ==&lt;br /&gt;
In earlier times, all the metadata about each experiment would be kept in laboratory notebooks. This method is reaching the end of its useful lifetime. There is too much data, and physical notebooks are not searchable by machine. If a later researcher studies the data, how are they going to know what it means? What sort of experiment was carried out? Who did the work? Where was it done? What were the objectives of the experiment? What code should be executed in order to process the data? The purpose of this project is to develop a relational database, which can be interrogated using Structures Query Language (SQL). The data will need to be harvested, re-formatted and checked using a scripting language. We are proposing the use of the Python3 programming language. Statistical post-processing of the data can be carried out in several languages, including MATLAB, Python3, or the “R” programming language.&lt;br /&gt;
There are number of Open-Source SQL data base packages for the Linux operating system, including Bee Keeper, Libre Office BASE, and Keri. Python3 will run under Linux. The early parts of the project would involve programming in a Linux environment.&lt;br /&gt;
In order to make the work realistic, students will measure a series of RC ladder circuits, using a Picoscope. This will generate large amounts of accurate sampled data, which will then need to be classified and processed. The experimental part of the project is safe and could be carried out off campus, in Adelaide. Remote students, outside of Adelaide, would have to concentrate on the software aspects of the project&lt;br /&gt;
&lt;br /&gt;
=== Project team ===&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Ruoyun Zhou&lt;br /&gt;
* Zeyu Fu&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* Dr Andrew Allison&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
=== Electrical principles used ===&lt;br /&gt;
There are three laws are used in this project, Ohm’s Law, Kirchhoff’s Current Law and Kirchhoff’s Voltage Law respectively. &lt;br /&gt;
Ohm’s Law is named for physicist Georg Ohm(1789-1854) from Germany. It aims to calculate the relationship between current, resistance and voltage in an electrical circuit. Voltage is the pressure that triggers flow of electrons, its unit is volt which is always abbreviated as (V). While current is the rate of electron flow, its unit is ampere or amp (A). The last variable is resistance which is the flow inhibitor, note that resistance is a constant as it is measured from the resistor, it does not change according to the voltage and current, resistor unit is ohm(). The formula of Ohm’s Law is voltage = current * resistance, which can be formulated as V=I*R in mathematics. From the formula if two variables values are known then the third one can be calculated by applying the mathematical formula. &lt;br /&gt;
Ohm’s Law is undoubtably the easiest tool for circuit analysis, however, voltages and currents will not be easily obtained when it comes to analyse complex circuits such as T or bridge networks, therefore, Kirchhoff’s Circuit Law comes in place for the calculation. Kirchhoff’s Circuit Law is developed by a German physicist Gustav Kirchhoff back in 1845 where it consists of two law, KCL and KVL. Kirchhoff’s Current Law is used to cope with the current flows around a closed circuit while Kirchhoff’s Voltage Law is used to cope with the voltage sources present in a closed circuit.  Kirchhoff’s Current Law is also referred as Kirchhoff’s First Law and it claims that “total current charge entering a junction or node is exactly equal to the charge leaving the node as it has no other place to go except to leave, as no charge is lost within the node”. The previous sentence can be summarised in a mathematical form as: I_exiting+I_entering=0. This Kirchhoff’s Current Law is known as Conservation of Charge. &lt;br /&gt;
Note that the electrical terminology node refers to a junction of two or more current carrying paths or elements, e.g. components and cables. Kirchhoff’s Current Law will be applicable for parallel circuits analysis only if a closed circuit exist. &lt;br /&gt;
Kirchhoff’s Voltage Law is Kirchhoff’s Second Law, it claims “in any closed loop network, the total voltage around the loop is equal to the sum of all the voltage drops within the same loop” which is also equivalent to zero. It can be seen in mathematical as the sum of all voltages in the loop must equivalent to zero. This is known as Conservation of Energy. &lt;br /&gt;
All voltage will be looping in the same direction, it will be either positive or negative and eventually returning to the original starting point. The reason why the direction is important is if it is not the summation of all voltage will not be equivalent to zero.&lt;br /&gt;
Whenever there is a phase angle there will be power component called reactive power, it is also referred as imaginary power, it is described in a unit called “volt-amperes reactive”, (VAr). The reactive power, Var, represents the products of amperes and volts which are out-of-phase with each other instead of representing the actual power. Reactive power is the fraction of electricity which alternate current equipment in order to help to sustain and establish the electric and magnetic fields required. Phase angle or phase shift between the current and voltage will affect the amount of reactive power present in an AC circuit. Reactive power is negative when it is “consumed” and it is positive when it is “supplied”. Nowadays, reactive power is adopted by majority types of electrical equipment which uses a magnetic field. For example, transformers, motors and generators. Reactive power is indispensable when overhead power transmission lines experienced reactive losses.&lt;br /&gt;
&lt;br /&gt;
== Error Estimation ==&lt;br /&gt;
assume that there is a simple linear regression model with the equation as y=β_0+β_1 X+e. Where X is an independent variable and y is the dependent variable. β_0 and β_1 are the intercept term and slope parameter in the equation, they are also deemed as regression coefficients. The failure of data to lie on the straight line and represents the difference between the observed realizations and true of y is described as e which is the unobservable error component in the above equation. However, e is assumed to be observed as identically distributed and independent random variable with the constant variance σ^2 and mean zero characteristics for the reason of statistical inferences. The independent variable is considered as non-stochastic where y is deemed as a random variable with E(y)=β_0+β_1 X and var(y)=σ^2 because it is considered to be controlled by the experimenter. X can be a random variable sometimes, and in that case, the conditional mean of y given X=x will be E(y│x)=β_0+β_1 X and the conditional variance of y given X=x will be var(y|x)=σ^2 instead of simple variance of y and simple mean. The term e is unobserved and β_0,β_1,σ^2  are usually unknown. However, to determine the unknown parameters T pairs of observations (x_t,y_t )(t=1,…,T) on (X,y) are obtained. There are numerous methods of estimation can be used to confirm the estimates of the parameters, and maximum likelihood principles and least squares are the most popular methods of estimation. &lt;br /&gt;
The Least Square Estimation can be illustrated as a sample of T sets of observations (x_t,y_t) (t=1,…,T) and based on the previous paragraph it can be written as &lt;br /&gt;
y_t=β_0+β_1 x_t+e_t  (t=1,…,T)&lt;br /&gt;
The principle of least square is to ensure that the sum of squares of difference between the line in the scatter diagram and the observations is minimum by aiming to estimate β_0,β_1. This idea is deemed from various perspectives. The direct regression method is to obtain the estimates of β_0,β_1 at the time being where the vertical difference between the line in the scatter diagram and the observations and its sum of squares is deemed as minimized. The terms β_0,β_1 are obtained through deeming the sum of the absolute deviation of the observations from the line in the vertical direction in the scatter diagram by using the least absolute regression method.&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;br /&gt;
&lt;br /&gt;
[2] ...&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2020s2-7511_SQL_Database_for_Experimental_Metadata&amp;diff=16233</id>
		<title>Projects:2020s2-7511 SQL Database for Experimental Metadata</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2020s2-7511_SQL_Database_for_Experimental_Metadata&amp;diff=16233"/>
		<updated>2021-06-04T06:15:40Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Topic 1 */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:2020s2-7511 SQL Database for Experimental Metadata]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2020 s2|7511 SQL Database for Experimental Metadata]]&lt;br /&gt;
Abstract here&lt;br /&gt;
== Introduction ==&lt;br /&gt;
In earlier times, all the metadata about each experiment would be kept in laboratory notebooks. This method is reaching the end of its useful lifetime. There is too much data, and physical notebooks are not searchable by machine. If a later researcher studies the data, how are they going to know what it means? What sort of experiment was carried out? Who did the work? Where was it done? What were the objectives of the experiment? What code should be executed in order to process the data? The purpose of this project is to develop a relational database, which can be interrogated using Structures Query Language (SQL). The data will need to be harvested, re-formatted and checked using a scripting language. We are proposing the use of the Python3 programming language. Statistical post-processing of the data can be carried out in several languages, including MATLAB, Python3, or the “R” programming language.&lt;br /&gt;
There are number of Open-Source SQL data base packages for the Linux operating system, including Bee Keeper, Libre Office BASE, and Keri. Python3 will run under Linux. The early parts of the project would involve programming in a Linux environment.&lt;br /&gt;
In order to make the work realistic, students will measure a series of RC ladder circuits, using a Picoscope. This will generate large amounts of accurate sampled data, which will then need to be classified and processed. The experimental part of the project is safe and could be carried out off campus, in Adelaide. Remote students, outside of Adelaide, would have to concentrate on the software aspects of the project&lt;br /&gt;
&lt;br /&gt;
=== Project team ===&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Ruoyun Zhou&lt;br /&gt;
* Zeyu Fu&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* Dr Andrew Allison&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
=== Electrical principles used ===&lt;br /&gt;
There are three laws are used in this project, Ohm’s Law, Kirchhoff’s Current Law and Kirchhoff’s Voltage Law respectively. &lt;br /&gt;
Ohm’s Law is named for physicist Georg Ohm(1789-1854) from Germany. It aims to calculate the relationship between current, resistance and voltage in an electrical circuit. Voltage is the pressure that triggers flow of electrons, its unit is volt which is always abbreviated as (V). While current is the rate of electron flow, its unit is ampere or amp (A). The last variable is resistance which is the flow inhibitor, note that resistance is a constant as it is measured from the resistor, it does not change according to the voltage and current, resistor unit is ohm(). The formula of Ohm’s Law is voltage = current * resistance, which can be formulated as V=I*R in mathematics. From the formula if two variables values are known then the third one can be calculated by applying the mathematical formula. &lt;br /&gt;
Ohm’s Law is undoubtably the easiest tool for circuit analysis, however, voltages and currents will not be easily obtained when it comes to analyse complex circuits such as T or bridge networks, therefore, Kirchhoff’s Circuit Law comes in place for the calculation. Kirchhoff’s Circuit Law is developed by a German physicist Gustav Kirchhoff back in 1845 where it consists of two law, KCL and KVL. Kirchhoff’s Current Law is used to cope with the current flows around a closed circuit while Kirchhoff’s Voltage Law is used to cope with the voltage sources present in a closed circuit.  Kirchhoff’s Current Law is also referred as Kirchhoff’s First Law and it claims that “total current charge entering a junction or node is exactly equal to the charge leaving the node as it has no other place to go except to leave, as no charge is lost within the node”. The previous sentence can be summarised in a mathematical form as: I_exiting+I_entering=0. This Kirchhoff’s Current Law is known as Conservation of Charge. &lt;br /&gt;
Note that the electrical terminology node refers to a junction of two or more current carrying paths or elements, e.g. components and cables. Kirchhoff’s Current Law will be applicable for parallel circuits analysis only if a closed circuit exist. &lt;br /&gt;
Kirchhoff’s Voltage Law is Kirchhoff’s Second Law, it claims “in any closed loop network, the total voltage around the loop is equal to the sum of all the voltage drops within the same loop” which is also equivalent to zero. It can be seen in mathematical as the sum of all voltages in the loop must equivalent to zero. This is known as Conservation of Energy. &lt;br /&gt;
All voltage will be looping in the same direction, it will be either positive or negative and eventually returning to the original starting point. The reason why the direction is important is if it is not the summation of all voltage will not be equivalent to zero.&lt;br /&gt;
Whenever there is a phase angle there will be power component called reactive power, it is also referred as imaginary power, it is described in a unit called “volt-amperes reactive”, (VAr). The reactive power, Var, represents the products of amperes and volts which are out-of-phase with each other instead of representing the actual power. Reactive power is the fraction of electricity which alternate current equipment in order to help to sustain and establish the electric and magnetic fields required. Phase angle or phase shift between the current and voltage will affect the amount of reactive power present in an AC circuit. Reactive power is negative when it is “consumed” and it is positive when it is “supplied”. Nowadays, reactive power is adopted by majority types of electrical equipment which uses a magnetic field. For example, transformers, motors and generators. Reactive power is indispensable when overhead power transmission lines experienced reactive losses.&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;br /&gt;
&lt;br /&gt;
[2] ...&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2020s2-7511_SQL_Database_for_Experimental_Metadata&amp;diff=16232</id>
		<title>Projects:2020s2-7511 SQL Database for Experimental Metadata</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2020s2-7511_SQL_Database_for_Experimental_Metadata&amp;diff=16232"/>
		<updated>2021-06-04T06:15:08Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Background */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:2020s2-7511 SQL Database for Experimental Metadata]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2020 s2|7511 SQL Database for Experimental Metadata]]&lt;br /&gt;
Abstract here&lt;br /&gt;
== Introduction ==&lt;br /&gt;
In earlier times, all the metadata about each experiment would be kept in laboratory notebooks. This method is reaching the end of its useful lifetime. There is too much data, and physical notebooks are not searchable by machine. If a later researcher studies the data, how are they going to know what it means? What sort of experiment was carried out? Who did the work? Where was it done? What were the objectives of the experiment? What code should be executed in order to process the data? The purpose of this project is to develop a relational database, which can be interrogated using Structures Query Language (SQL). The data will need to be harvested, re-formatted and checked using a scripting language. We are proposing the use of the Python3 programming language. Statistical post-processing of the data can be carried out in several languages, including MATLAB, Python3, or the “R” programming language.&lt;br /&gt;
There are number of Open-Source SQL data base packages for the Linux operating system, including Bee Keeper, Libre Office BASE, and Keri. Python3 will run under Linux. The early parts of the project would involve programming in a Linux environment.&lt;br /&gt;
In order to make the work realistic, students will measure a series of RC ladder circuits, using a Picoscope. This will generate large amounts of accurate sampled data, which will then need to be classified and processed. The experimental part of the project is safe and could be carried out off campus, in Adelaide. Remote students, outside of Adelaide, would have to concentrate on the software aspects of the project&lt;br /&gt;
&lt;br /&gt;
=== Project team ===&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Ruoyun Zhou&lt;br /&gt;
* Zeyu Fu&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* Dr Andrew Allison&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
=== Topic 1 ===&lt;br /&gt;
There are three laws are used in this project, Ohm’s Law, Kirchhoff’s Current Law and Kirchhoff’s Voltage Law respectively. &lt;br /&gt;
Ohm’s Law is named for physicist Georg Ohm(1789-1854) from Germany. It aims to calculate the relationship between current, resistance and voltage in an electrical circuit. Voltage is the pressure that triggers flow of electrons, its unit is volt which is always abbreviated as (V). While current is the rate of electron flow, its unit is ampere or amp (A). The last variable is resistance which is the flow inhibitor, note that resistance is a constant as it is measured from the resistor, it does not change according to the voltage and current, resistor unit is ohm(). The formula of Ohm’s Law is voltage = current * resistance, which can be formulated as V=I*R in mathematics. From the formula if two variables values are known then the third one can be calculated by applying the mathematical formula. &lt;br /&gt;
Ohm’s Law is undoubtably the easiest tool for circuit analysis, however, voltages and currents will not be easily obtained when it comes to analyse complex circuits such as T or bridge networks, therefore, Kirchhoff’s Circuit Law comes in place for the calculation. Kirchhoff’s Circuit Law is developed by a German physicist Gustav Kirchhoff back in 1845 where it consists of two law, KCL and KVL. Kirchhoff’s Current Law is used to cope with the current flows around a closed circuit while Kirchhoff’s Voltage Law is used to cope with the voltage sources present in a closed circuit.  Kirchhoff’s Current Law is also referred as Kirchhoff’s First Law and it claims that “total current charge entering a junction or node is exactly equal to the charge leaving the node as it has no other place to go except to leave, as no charge is lost within the node”. The previous sentence can be summarised in a mathematical form as: I_exiting+I_entering=0. This Kirchhoff’s Current Law is known as Conservation of Charge. &lt;br /&gt;
Note that the electrical terminology node refers to a junction of two or more current carrying paths or elements, e.g. components and cables. Kirchhoff’s Current Law will be applicable for parallel circuits analysis only if a closed circuit exist. &lt;br /&gt;
Kirchhoff’s Voltage Law is Kirchhoff’s Second Law, it claims “in any closed loop network, the total voltage around the loop is equal to the sum of all the voltage drops within the same loop” which is also equivalent to zero. It can be seen in mathematical as the sum of all voltages in the loop must equivalent to zero. This is known as Conservation of Energy. &lt;br /&gt;
All voltage will be looping in the same direction, it will be either positive or negative and eventually returning to the original starting point. The reason why the direction is important is if it is not the summation of all voltage will not be equivalent to zero.&lt;br /&gt;
Whenever there is a phase angle there will be power component called reactive power, it is also referred as imaginary power, it is described in a unit called “volt-amperes reactive”, (VAr). The reactive power, Var, represents the products of amperes and volts which are out-of-phase with each other instead of representing the actual power. Reactive power is the fraction of electricity which alternate current equipment in order to help to sustain and establish the electric and magnetic fields required. Phase angle or phase shift between the current and voltage will affect the amount of reactive power present in an AC circuit. Reactive power is negative when it is “consumed” and it is positive when it is “supplied”. Nowadays, reactive power is adopted by majority types of electrical equipment which uses a magnetic field. For example, transformers, motors and generators. Reactive power is indispensable when overhead power transmission lines experienced reactive losses.&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;br /&gt;
&lt;br /&gt;
[2] ...&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14643</id>
		<title>Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14643"/>
		<updated>2020-06-08T10:11:56Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Method */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:Projects]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2018s1|106]]&lt;br /&gt;
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA&lt;br /&gt;
== Introduction ==&lt;br /&gt;
Project description here&lt;br /&gt;
&lt;br /&gt;
=== Project team === Group 25601&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Rui Yang&lt;br /&gt;
* Mohamad Hafiz Mohamad Rodzi&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
* Sayed Mohd Amir Shahirudin Sayed Sagar&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* A/Prof. Cornelis Keith Kikkert&lt;br /&gt;
* Said Al-Sarawi&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
To Implement floating-point algorithm as fixed-point algorithm in FPGA&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
&lt;br /&gt;
== IIR Filter ==&lt;br /&gt;
&lt;br /&gt;
This topic presents the development of the IIR filter towards the implementation of FPGA.&lt;br /&gt;
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited&lt;br /&gt;
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer&lt;br /&gt;
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE&lt;br /&gt;
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power&lt;br /&gt;
systems. This section shows the VHDL routines designed in the Quartus Prime software&lt;br /&gt;
based on the MATLAB algorithm. VHDL is a hardware description language used to&lt;br /&gt;
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point&lt;br /&gt;
standard. The operations are carried on mantissa, exponents, and sign components. This&lt;br /&gt;
includes the routine to convert the filter coefficients from the algorithms in a signed&lt;br /&gt;
floating-point format.&lt;br /&gt;
&lt;br /&gt;
=== Literature Review ===&lt;br /&gt;
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref&lt;br /&gt;
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating&lt;br /&gt;
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the&lt;br /&gt;
voltage and current analog inputs before the computation begins. Ref [8] reports that&lt;br /&gt;
their PMU design is using the window method of FIR filter. The performance of the filter&lt;br /&gt;
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth&lt;br /&gt;
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main&lt;br /&gt;
frequency&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving  a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.&lt;br /&gt;
Frequency Lock Loop(FLL):		 	 	 		Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC. &lt;br /&gt;
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured  from the BNC connector, therefore a division of 2 algorithm will be performed.&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
The result of 10 mhzs generation is shown below &lt;br /&gt;
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
The result of DAC sawtooth waveform is shown below &lt;br /&gt;
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
The result of the FLL is shown below&lt;br /&gt;
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
The result of the time/date stamp are displayed below&lt;br /&gt;
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14641</id>
		<title>Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14641"/>
		<updated>2020-06-08T10:10:43Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Results */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:Projects]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2018s1|106]]&lt;br /&gt;
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA&lt;br /&gt;
== Introduction ==&lt;br /&gt;
Project description here&lt;br /&gt;
&lt;br /&gt;
=== Project team === Group 25601&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Rui Yang&lt;br /&gt;
* Mohamad Hafiz Mohamad Rodzi&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
* Sayed Mohd Amir Shahirudin Sayed Sagar&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* A/Prof. Cornelis Keith Kikkert&lt;br /&gt;
* Said Al-Sarawi&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
To Implement floating-point algorithm as fixed-point algorithm in FPGA&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
&lt;br /&gt;
== IIR Filter ==&lt;br /&gt;
&lt;br /&gt;
This topic presents the development of the IIR filter towards the implementation of FPGA.&lt;br /&gt;
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited&lt;br /&gt;
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer&lt;br /&gt;
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE&lt;br /&gt;
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power&lt;br /&gt;
systems. This section shows the VHDL routines designed in the Quartus Prime software&lt;br /&gt;
based on the MATLAB algorithm. VHDL is a hardware description language used to&lt;br /&gt;
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point&lt;br /&gt;
standard. The operations are carried on mantissa, exponents, and sign components. This&lt;br /&gt;
includes the routine to convert the filter coefficients from the algorithms in a signed&lt;br /&gt;
floating-point format.&lt;br /&gt;
&lt;br /&gt;
=== Literature Review ===&lt;br /&gt;
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref&lt;br /&gt;
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating&lt;br /&gt;
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the&lt;br /&gt;
voltage and current analog inputs before the computation begins. Ref [8] reports that&lt;br /&gt;
their PMU design is using the window method of FIR filter. The performance of the filter&lt;br /&gt;
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth&lt;br /&gt;
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main&lt;br /&gt;
frequency&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
The result of 10 mhzs generation is shown below &lt;br /&gt;
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
The result of DAC sawtooth waveform is shown below &lt;br /&gt;
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
The result of the FLL is shown below&lt;br /&gt;
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
The result of the time/date stamp are displayed below&lt;br /&gt;
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:0C129181-DEFC-44F4-86E1-E55D648C6D7F_4_5005_c.jpg&amp;diff=14640</id>
		<title>File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:0C129181-DEFC-44F4-86E1-E55D648C6D7F_4_5005_c.jpg&amp;diff=14640"/>
		<updated>2020-06-08T10:10:36Z</updated>

		<summary type="html">&lt;p&gt;A1702535: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;time/date&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg&amp;diff=14636</id>
		<title>File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg&amp;diff=14636"/>
		<updated>2020-06-08T10:09:52Z</updated>

		<summary type="html">&lt;p&gt;A1702535: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FLL&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:91F904F0-21DA-48C4-B0B2-073DC2BF7505_4_5005_c.jpg&amp;diff=14634</id>
		<title>File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:91F904F0-21DA-48C4-B0B2-073DC2BF7505_4_5005_c.jpg&amp;diff=14634"/>
		<updated>2020-06-08T10:09:06Z</updated>

		<summary type="html">&lt;p&gt;A1702535: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;DAC&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4_4_5005_c.jpg&amp;diff=14632</id>
		<title>File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4_4_5005_c.jpg&amp;diff=14632"/>
		<updated>2020-06-08T10:08:38Z</updated>

		<summary type="html">&lt;p&gt;A1702535: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;10mhz&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14629</id>
		<title>Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14629"/>
		<updated>2020-06-08T10:04:29Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Conclusion */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:Projects]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2018s1|106]]&lt;br /&gt;
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA&lt;br /&gt;
== Introduction ==&lt;br /&gt;
Project description here&lt;br /&gt;
&lt;br /&gt;
=== Project team === Group 25601&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Rui Yang&lt;br /&gt;
* Mohamad Hafiz Mohamad Rodzi&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
* Sayed Mohd Amir Shahirudin Sayed Sagar&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* A/Prof. Cornelis Keith Kikkert&lt;br /&gt;
* Said Al-Sarawi&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
To Implement floating-point algorithm as fixed-point algorithm in FPGA&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
&lt;br /&gt;
== IIR Filter ==&lt;br /&gt;
&lt;br /&gt;
This topic presents the development of the IIR filter towards the implementation of FPGA.&lt;br /&gt;
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited&lt;br /&gt;
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer&lt;br /&gt;
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE&lt;br /&gt;
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power&lt;br /&gt;
systems. This section shows the VHDL routines designed in the Quartus Prime software&lt;br /&gt;
based on the MATLAB algorithm. VHDL is a hardware description language used to&lt;br /&gt;
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point&lt;br /&gt;
standard. The operations are carried on mantissa, exponents, and sign components. This&lt;br /&gt;
includes the routine to convert the filter coefficients from the algorithms in a signed&lt;br /&gt;
floating-point format.&lt;br /&gt;
&lt;br /&gt;
=== Literature Review ===&lt;br /&gt;
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref&lt;br /&gt;
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating&lt;br /&gt;
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the&lt;br /&gt;
voltage and current analog inputs before the computation begins. Ref [8] reports that&lt;br /&gt;
their PMU design is using the window method of FIR filter. The performance of the filter&lt;br /&gt;
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth&lt;br /&gt;
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main&lt;br /&gt;
frequency&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14342</id>
		<title>Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14342"/>
		<updated>2020-06-07T09:45:53Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Project team */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:Projects]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2018s1|106]]&lt;br /&gt;
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA&lt;br /&gt;
== Introduction ==&lt;br /&gt;
Project description here&lt;br /&gt;
&lt;br /&gt;
=== Project team === Group 25601&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Rui Yang&lt;br /&gt;
* Mohamad Hafiz Mohamad Rodzi&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
* Sayed Mohd Amir Shahirudin Sayed Sagar&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* A/Prof. Cornelis Keith Kikkert&lt;br /&gt;
* Said Al-Sarawi&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
To Implement floating-point algorithm as fixed-point algorithm in FPGA&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
&lt;br /&gt;
== IIR Filter ==&lt;br /&gt;
&lt;br /&gt;
This topic presents the development of the IIR filter towards the implementation of FPGA.&lt;br /&gt;
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited&lt;br /&gt;
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer&lt;br /&gt;
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE&lt;br /&gt;
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power&lt;br /&gt;
systems. This section shows the VHDL routines designed in the Quartus Prime software&lt;br /&gt;
based on the MATLAB algorithm. VHDL is a hardware description language used to&lt;br /&gt;
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point&lt;br /&gt;
standard. The operations are carried on mantissa, exponents, and sign components. This&lt;br /&gt;
includes the routine to convert the filter coefficients from the algorithms in a signed&lt;br /&gt;
floating-point format.&lt;br /&gt;
&lt;br /&gt;
=== Literature Review ===&lt;br /&gt;
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref&lt;br /&gt;
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating&lt;br /&gt;
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the&lt;br /&gt;
voltage and current analog inputs before the computation begins. Ref [8] reports that&lt;br /&gt;
their PMU design is using the window method of FIR filter. The performance of the filter&lt;br /&gt;
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth&lt;br /&gt;
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main&lt;br /&gt;
frequency&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14338</id>
		<title>Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14338"/>
		<updated>2020-06-07T09:40:35Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Project students */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:Projects]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2018s1|106]]&lt;br /&gt;
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA&lt;br /&gt;
== Introduction ==&lt;br /&gt;
Project description here&lt;br /&gt;
&lt;br /&gt;
=== Project team ===&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Rui Yang&lt;br /&gt;
* Mohamad Hafiz Mohamad Rodzi&lt;br /&gt;
* Junwen Zheng&lt;br /&gt;
* Sayed Mohd Amir Shahirudin Sayed Sagar&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* A/Prof. Cornelis Keith Kikkert&lt;br /&gt;
* Said Al-Sarawi&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
To Implement floating-point algorithm as fixed-point algorithm in FPGA&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
&lt;br /&gt;
== IIR Filter ==&lt;br /&gt;
&lt;br /&gt;
This topic presents the development of the IIR filter towards the implementation of FPGA.&lt;br /&gt;
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited&lt;br /&gt;
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer&lt;br /&gt;
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE&lt;br /&gt;
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power&lt;br /&gt;
systems. This section shows the VHDL routines designed in the Quartus Prime software&lt;br /&gt;
based on the MATLAB algorithm. VHDL is a hardware description language used to&lt;br /&gt;
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point&lt;br /&gt;
standard. The operations are carried on mantissa, exponents, and sign components. This&lt;br /&gt;
includes the routine to convert the filter coefficients from the algorithms in a signed&lt;br /&gt;
floating-point format.&lt;br /&gt;
&lt;br /&gt;
=== Literature Review ===&lt;br /&gt;
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref&lt;br /&gt;
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating&lt;br /&gt;
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the&lt;br /&gt;
voltage and current analog inputs before the computation begins. Ref [8] reports that&lt;br /&gt;
their PMU design is using the window method of FIR filter. The performance of the filter&lt;br /&gt;
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth&lt;br /&gt;
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main&lt;br /&gt;
frequency&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
	<entry>
		<id>https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14337</id>
		<title>Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation</title>
		<link rel="alternate" type="text/html" href="https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2019s2-25601_Phasor_Measurement_Unit:_FPGA_Implementation&amp;diff=14337"/>
		<updated>2020-06-07T09:39:27Z</updated>

		<summary type="html">&lt;p&gt;A1702535: /* Project students */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Category:Projects]]&lt;br /&gt;
[[Category:Final Year Projects]]&lt;br /&gt;
[[Category:2018s1|106]]&lt;br /&gt;
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA&lt;br /&gt;
== Introduction ==&lt;br /&gt;
Project description here&lt;br /&gt;
&lt;br /&gt;
=== Project team ===&lt;br /&gt;
==== Project students ====&lt;br /&gt;
* Rui Yang&lt;br /&gt;
* Mohamad Hafiz Mohamad Rodzi&lt;br /&gt;
* JunWen Zheng&lt;br /&gt;
* Sayed Mohd Amir Shahirudin Sayed Sagar&lt;br /&gt;
&lt;br /&gt;
==== Supervisors ====&lt;br /&gt;
* A/Prof. Cornelis Keith Kikkert&lt;br /&gt;
* Said Al-Sarawi&lt;br /&gt;
&lt;br /&gt;
==== Advisors ====&lt;br /&gt;
*&lt;br /&gt;
*&lt;br /&gt;
&lt;br /&gt;
=== Objectives ===&lt;br /&gt;
Set of objectives&lt;br /&gt;
To Implement floating-point algorithm as fixed-point algorithm in FPGA&lt;br /&gt;
&lt;br /&gt;
== Background ==&lt;br /&gt;
&lt;br /&gt;
== IIR Filter ==&lt;br /&gt;
&lt;br /&gt;
This topic presents the development of the IIR filter towards the implementation of FPGA.&lt;br /&gt;
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited&lt;br /&gt;
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer&lt;br /&gt;
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE&lt;br /&gt;
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power&lt;br /&gt;
systems. This section shows the VHDL routines designed in the Quartus Prime software&lt;br /&gt;
based on the MATLAB algorithm. VHDL is a hardware description language used to&lt;br /&gt;
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point&lt;br /&gt;
standard. The operations are carried on mantissa, exponents, and sign components. This&lt;br /&gt;
includes the routine to convert the filter coefficients from the algorithms in a signed&lt;br /&gt;
floating-point format.&lt;br /&gt;
&lt;br /&gt;
=== Literature Review ===&lt;br /&gt;
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref&lt;br /&gt;
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating&lt;br /&gt;
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the&lt;br /&gt;
voltage and current analog inputs before the computation begins. Ref [8] reports that&lt;br /&gt;
their PMU design is using the window method of FIR filter. The performance of the filter&lt;br /&gt;
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth&lt;br /&gt;
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main&lt;br /&gt;
frequency&lt;br /&gt;
&lt;br /&gt;
== Method ==&lt;br /&gt;
&lt;br /&gt;
== Results ==&lt;br /&gt;
&lt;br /&gt;
== Conclusion ==&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
[1] a, b, c, &amp;quot;Simple page&amp;quot;, In Proceedings of the Conference of Simpleness, 2010.&lt;/div&gt;</summary>
		<author><name>A1702535</name></author>
		
	</entry>
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