Projects - User contributions [en]

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2020-06-09T01:09:11Z

A1757608: /* LabView Data Display */

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
== Introduction ==

Phasor Measurement Units (PMUs) are used by the power industry to measure Voltage, Phase, Frequency and Rate of Change of Frequency (RoCoF) of the power system. The IEEE standard requires these measurements to be available within 2 mains cycles (40 mS) of the waveform sampling time. These PMU’s are an integral part of keeping the power system stable by controlling circuit breakers and generator settings in a high level of renewable power supply grid. Implementing the PMU algorithm in an FPGA is required to ensure the speed of operation and reliability required for this critical instrumentation.During 2018, Dr. Kikkert used Matlab to develop an algorithm to perform the PMU calculations quicker and with better accuracy than is possible at present. Hardware to digitise the 3 phase mains voltages has just been completed by Thesis students. This project aims to implement the floating point Matlab algorithm as a fixed point algorithm on a DE10-Lite FPGA development board from Terasic, using VHDL or Verilog. The code to be produced is to read the data from the digital to analogue converters on the existing hardware, calculate the Voltage, Phase, Frequency and RoCoF and send this data to a computer to be displayed using existing Labview code.As a second priority task, for higher grades, the same FPGA board is to be used with an available GPS receiver and existing hardware to produce a GPS time stamp for the Voltage, Phase, Frequency and RoCoF data.

=== Project Group 25601 ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* Junwen Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar

==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Dr. Said Al-Sarawi

=== Objectives ===
This project aims to achieve goals as follow:

1. To produce a fully working Phasor Measurement Unit.
2. Implement floating point Matlab algorithm in FPGA.
3. Calculate Voltage ,Phase , Frequency and RoCoF with a GPS time stamp.
4. Meet the requirement of IEEE/IEC standards.

== Background ==
Project Overview
[[File: Overview of the project.png|thumb|Project Overview]]
Three-phase 50 Hz waveforms are applied to the analogue input of the hardware circuit that was designed by Kikkert. The hardware includes a 6 channel ADC chip with 16 bits accuracy. The waveforms are sampled by the ADC chip at 10 kHz sampling rate for a 50 Hz main and can be changed to 60 Hz mains. The frequency lock loop circuit that synchronized with the GPS provides accurate sampling frequency for the ADC. The waveforms sampled by the ADC chip are digitised as 16 bits twos-complement.
Digitised waveforms are shifted to the baseband signal by multiplying with the 50 Hz quadrature signal (Cosine and Sine) that generated by the oscillator which is synchronized with the GPS. The quadrature signals are digitally synthesized by Lookup Table (LuT). The nominal quadrature signals are created for each phase A, B, and C with ± 120° phase difference with each phase. I and Q signals produced by the multiplication are filtered using averaging filters. The voltage magnitude is obtained from equation (1):
V=√(I^2+Q^2 ) (1)
The phase is obtained from equation (2):
Phase=atan⁡(I/Q) (2)
. The square root and inverse function to calculate voltage and phase are achieved in FPGA using interpolation. The calculated voltage magnitude and phase are filtered with IIR filter to attenuate the 2nd order harmonic and above. To get the accurate voltage magnitude, voltage correction is implemented due to the Sinc function of the rectangular filter. The frequency value of the phasor is calculated by doing a differentiation of the phase value. The RoCoF is calculated by differentiation of the calculated frequency. The values of Voltage, Frequency, RoCoF, and timestamp are displayed on Labview.
== IQ Demodulation ==
[[File:Quarter.png|thumb]]
To obtain real and imaginary information of the phasor the input waveform needs to be down-convert
ed. The IQ down-conversion will utilise quadrature signals that generated from the previous sections. The process of IQ down-conversion will cause the signals to be in the baseband region.

The digitised 16 bits input from the ADC is multiplied with quadrature signals generated from the LuT. The multiplication process utilises the 18-bit x 18-bit embedded multiplier inside the MAX10. Although there many multiplication algorithms that can be implemented such as Booth multiplication algorithms, using the embedded multiplier prove to be the easiest to implement. The embedded multipliers take account the signed integer during the multiplication process. There no need for an extra algorithm to sort the signed bits for the multiplication.

== IIR Filter ==
[[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

This topic presents the development of the IIR filter towards the implementation of FPGA.
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power
systems. This section shows the VHDL routines designed in the Quartus Prime software
based on the MATLAB algorithm. VHDL is a hardware description language used to
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point
standard. The operations are carried on mantissa, exponents, and sign components. This
includes the routine to convert the filter coefficients from the algorithms in a signed
floating-point format.

=== Literature Review ===
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the
voltage and current analog inputs before the computation begins. Ref [8] reports that
their PMU design is using the window method of FIR filter. The performance of the filter
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main
frequency

== Method ==

=== Implementation of IIR Filter ===
[[File:Single Precision IEEE 754 Floating-Point Standard.png|300px|frame|centre|Single Precision IEEE 754 Floating-Point Standard]]
 
==== Floating point addition operation ====

The addition operation is performed based on the steps as follows:

1. Smaller exponent number is rewritten to match with the larger exponent number.
 
2. Adding of the mantissas.
 
3. Normalise the sum and checking process for the underflow and overflow.
 
4. Rounding the sum.

The state machine of the addition operation is explained here. The operation is halted and
wait for the request signal goes high. If the signal is true, the input will enter exponent
alignment process. The exponents of both input signals are set as unsigned
std_logic_vector to make the comparison. The mantissa that having smaller exponent
value will be downshifted based on the different value of the comparison. To do the
comparison, the unsigned exponent value is converted to signed value. Then, the
downshifting of the mantissa is done in integer form of the exponent different.
In normalisation process, the overflow sum is downshifted by dropping the least
significant bit.

 
==== Floating point multiplication operation ====

The multiplication operation is performed based on the steps as follows:

1. The addition of exponents to find new exponent. The biased exponents are added
twice and need to subtract it once afterward to compensate.
 
2. The multiplication of mantissas.
 
3. Normalise the product.14
 
4. Round the result.

The operation starts when the request input signal goes high. The inputs are loaded and
are multiplied with each other. Then, the normalisation process is done. Here, the
overflow of the product is checked. The result will in the form of sign, exponent, and
mantissa.

=== Establishing FPGA Communication to host PC ===
[[File:FPGA to PC block diagram.png|300px|frame|center|FPGA to PC block diagram]]
 
The FPGA communication to host PC is established by using JTAG to Avalon MM Bridge
embedded IP core provided in Quartus Prime Lite. The block diagram shown in Figure
is the design approach that is used to establish the communication link between the DE10
board and the host PC. The design required the Altera serial JTAG cable (USB-Blaster)
connected between the JTAG port on the board and a host computer running the Quartus
Prime Programmer for the duration of the hardware duration period.

[[File:Platform Designer.png|300px|thumb|centre|Platform Designer]]
The first step is to create the hardware part of the block diagram. The block diagram
shown in Figure aboce can be instantiated in Platform Designer (Quartus Prime Menu > Tools
> Platform Designer). Figure here shows a complete structure of the big block in Figure above designed
in the Platform Designer. Noted that, JTAG to Avalon Master Bridge is the only master and
other peripherals are the slaves. By assigning the unique base addresses for each of the
components, the interaction between them can simply be done by calling the specific
address of the peripheral and the master component can read or write the instruction.
The read and write are done in System Console or Tcl script.

=== Global Positioning System ===

Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.
Frequency Lock Loop(FLL): Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC.
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured from the BNC connector, therefore a division of 2 algorithm will be performed.

== Results ==
=== FLL Results ===

The result of 10 mhzs generation is shown below
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]

The result of DAC sawtooth waveform is shown below
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]

The result of the FLL is shown below
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]

The result of the time/date stamp are displayed below
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]

== Conclusion ==
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2020-06-09T01:07:17Z

A1757608: /* LabView Data Display */

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
== Introduction ==

Phasor Measurement Units (PMUs) are used by the power industry to measure Voltage, Phase, Frequency and Rate of Change of Frequency (RoCoF) of the power system. The IEEE standard requires these measurements to be available within 2 mains cycles (40 mS) of the waveform sampling time. These PMU’s are an integral part of keeping the power system stable by controlling circuit breakers and generator settings in a high level of renewable power supply grid. Implementing the PMU algorithm in an FPGA is required to ensure the speed of operation and reliability required for this critical instrumentation.During 2018, Dr. Kikkert used Matlab to develop an algorithm to perform the PMU calculations quicker and with better accuracy than is possible at present. Hardware to digitise the 3 phase mains voltages has just been completed by Thesis students. This project aims to implement the floating point Matlab algorithm as a fixed point algorithm on a DE10-Lite FPGA development board from Terasic, using VHDL or Verilog. The code to be produced is to read the data from the digital to analogue converters on the existing hardware, calculate the Voltage, Phase, Frequency and RoCoF and send this data to a computer to be displayed using existing Labview code.As a second priority task, for higher grades, the same FPGA board is to be used with an available GPS receiver and existing hardware to produce a GPS time stamp for the Voltage, Phase, Frequency and RoCoF data.

=== Project Group 25601 ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* Junwen Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar

==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Dr. Said Al-Sarawi

=== Objectives ===
This project aims to achieve goals as follow:

1. To produce a fully working Phasor Measurement Unit.
2. Implement floating point Matlab algorithm in FPGA.
3. Calculate Voltage ,Phase , Frequency and RoCoF with a GPS time stamp.
4. Meet the requirement of IEEE/IEC standards.

== Background ==
Project Overview
[[File: Overview of the project.png|thumb|Project Overview]]
Three-phase 50 Hz waveforms are applied to the analogue input of the hardware circuit that was designed by Kikkert. The hardware includes a 6 channel ADC chip with 16 bits accuracy. The waveforms are sampled by the ADC chip at 10 kHz sampling rate for a 50 Hz main and can be changed to 60 Hz mains. The frequency lock loop circuit that synchronized with the GPS provides accurate sampling frequency for the ADC. The waveforms sampled by the ADC chip are digitised as 16 bits twos-complement.
Digitised waveforms are shifted to the baseband signal by multiplying with the 50 Hz quadrature signal (Cosine and Sine) that generated by the oscillator which is synchronized with the GPS. The quadrature signals are digitally synthesized by Lookup Table (LuT). The nominal quadrature signals are created for each phase A, B, and C with ± 120° phase difference with each phase. I and Q signals produced by the multiplication are filtered using averaging filters. The voltage magnitude is obtained from equation (1):
V=√(I^2+Q^2 ) (1)
The phase is obtained from equation (2):
Phase=atan⁡(I/Q) (2)
. The square root and inverse function to calculate voltage and phase are achieved in FPGA using interpolation. The calculated voltage magnitude and phase are filtered with IIR filter to attenuate the 2nd order harmonic and above. To get the accurate voltage magnitude, voltage correction is implemented due to the Sinc function of the rectangular filter. The frequency value of the phasor is calculated by doing a differentiation of the phase value. The RoCoF is calculated by differentiation of the calculated frequency. The values of Voltage, Frequency, RoCoF, and timestamp are displayed on Labview.
== IQ Demodulation ==
[[File:Quarter.png|thumb]]
To obtain real and imaginary information of the phasor the input waveform needs to be down-convert
ed. The IQ down-conversion will utilise quadrature signals that generated from the previous sections. The process of IQ down-conversion will cause the signals to be in the baseband region.

The digitised 16 bits input from the ADC is multiplied with quadrature signals generated from the LuT. The multiplication process utilises the 18-bit x 18-bit embedded multiplier inside the MAX10. Although there many multiplication algorithms that can be implemented such as Booth multiplication algorithms, using the embedded multiplier prove to be the easiest to implement. The embedded multipliers take account the signed integer during the multiplication process. There no need for an extra algorithm to sort the signed bits for the multiplication.

== IIR Filter ==
[[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

This topic presents the development of the IIR filter towards the implementation of FPGA.
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power
systems. This section shows the VHDL routines designed in the Quartus Prime software
based on the MATLAB algorithm. VHDL is a hardware description language used to
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point
standard. The operations are carried on mantissa, exponents, and sign components. This
includes the routine to convert the filter coefficients from the algorithms in a signed
floating-point format.

=== Literature Review ===
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the
voltage and current analog inputs before the computation begins. Ref [8] reports that
their PMU design is using the window method of FIR filter. The performance of the filter
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main
frequency

== Method ==

=== Implementation of IIR Filter ===
[[File:Single Precision IEEE 754 Floating-Point Standard.png|300px|frame|centre|Single Precision IEEE 754 Floating-Point Standard]]
 
==== Floating point addition operation ====

The addition operation is performed based on the steps as follows:

1. Smaller exponent number is rewritten to match with the larger exponent number.
 
2. Adding of the mantissas.
 
3. Normalise the sum and checking process for the underflow and overflow.
 
4. Rounding the sum.

The state machine of the addition operation is explained here. The operation is halted and
wait for the request signal goes high. If the signal is true, the input will enter exponent
alignment process. The exponents of both input signals are set as unsigned
std_logic_vector to make the comparison. The mantissa that having smaller exponent
value will be downshifted based on the different value of the comparison. To do the
comparison, the unsigned exponent value is converted to signed value. Then, the
downshifting of the mantissa is done in integer form of the exponent different.
In normalisation process, the overflow sum is downshifted by dropping the least
significant bit.

 
==== Floating point multiplication operation ====

The multiplication operation is performed based on the steps as follows:

1. The addition of exponents to find new exponent. The biased exponents are added
twice and need to subtract it once afterward to compensate.
 
2. The multiplication of mantissas.
 
3. Normalise the product.14
 
4. Round the result.

The operation starts when the request input signal goes high. The inputs are loaded and
are multiplied with each other. Then, the normalisation process is done. Here, the
overflow of the product is checked. The result will in the form of sign, exponent, and
mantissa.

=== Establishing FPGA Communication to host PC ===
[[File:FPGA to PC block diagram.png|300px|frame|center|FPGA to PC block diagram]]
 
The FPGA communication to host PC is established by using JTAG to Avalon MM Bridge
embedded IP core provided in Quartus Prime Lite. The block diagram shown in Figure
is the design approach that is used to establish the communication link between the DE10
board and the host PC. The design required the Altera serial JTAG cable (USB-Blaster)
connected between the JTAG port on the board and a host computer running the Quartus
Prime Programmer for the duration of the hardware duration period.

[[File:Platform Designer.png|300px|thumb|centre|Platform Designer]]
The first step is to create the hardware part of the block diagram. The block diagram
shown in Figure aboce can be instantiated in Platform Designer (Quartus Prime Menu > Tools
> Platform Designer). Figure here shows a complete structure of the big block in Figure above designed
in the Platform Designer. Noted that, JTAG to Avalon Master Bridge is the only master and
other peripherals are the slaves. By assigning the unique base addresses for each of the
components, the interaction between them can simply be done by calling the specific
address of the peripheral and the master component can read or write the instruction.
The read and write are done in System Console or Tcl script.

=== Global Positioning System ===

Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.
Frequency Lock Loop(FLL): Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC.
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured from the BNC connector, therefore a division of 2 algorithm will be performed.

== Results ==
=== LabView Data Display ===

<gallery>
Example.jpg|Caption1
Example.jpg|Caption2
</gallery>

=== FLL Results ===

The result of 10 mhzs generation is shown below
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]

The result of DAC sawtooth waveform is shown below
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]

The result of the FLL is shown below
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]

The result of the time/date stamp are displayed below
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]

== Conclusion ==
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2020-06-09T01:06:49Z

A1757608: /* Results */

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
== Introduction ==

Phasor Measurement Units (PMUs) are used by the power industry to measure Voltage, Phase, Frequency and Rate of Change of Frequency (RoCoF) of the power system. The IEEE standard requires these measurements to be available within 2 mains cycles (40 mS) of the waveform sampling time. These PMU’s are an integral part of keeping the power system stable by controlling circuit breakers and generator settings in a high level of renewable power supply grid. Implementing the PMU algorithm in an FPGA is required to ensure the speed of operation and reliability required for this critical instrumentation.During 2018, Dr. Kikkert used Matlab to develop an algorithm to perform the PMU calculations quicker and with better accuracy than is possible at present. Hardware to digitise the 3 phase mains voltages has just been completed by Thesis students. This project aims to implement the floating point Matlab algorithm as a fixed point algorithm on a DE10-Lite FPGA development board from Terasic, using VHDL or Verilog. The code to be produced is to read the data from the digital to analogue converters on the existing hardware, calculate the Voltage, Phase, Frequency and RoCoF and send this data to a computer to be displayed using existing Labview code.As a second priority task, for higher grades, the same FPGA board is to be used with an available GPS receiver and existing hardware to produce a GPS time stamp for the Voltage, Phase, Frequency and RoCoF data.

=== Project Group 25601 ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* Junwen Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar

==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Dr. Said Al-Sarawi

=== Objectives ===
This project aims to achieve goals as follow:

1. To produce a fully working Phasor Measurement Unit.
2. Implement floating point Matlab algorithm in FPGA.
3. Calculate Voltage ,Phase , Frequency and RoCoF with a GPS time stamp.
4. Meet the requirement of IEEE/IEC standards.

== Background ==
Project Overview
[[File: Overview of the project.png|thumb|Project Overview]]
Three-phase 50 Hz waveforms are applied to the analogue input of the hardware circuit that was designed by Kikkert. The hardware includes a 6 channel ADC chip with 16 bits accuracy. The waveforms are sampled by the ADC chip at 10 kHz sampling rate for a 50 Hz main and can be changed to 60 Hz mains. The frequency lock loop circuit that synchronized with the GPS provides accurate sampling frequency for the ADC. The waveforms sampled by the ADC chip are digitised as 16 bits twos-complement.
Digitised waveforms are shifted to the baseband signal by multiplying with the 50 Hz quadrature signal (Cosine and Sine) that generated by the oscillator which is synchronized with the GPS. The quadrature signals are digitally synthesized by Lookup Table (LuT). The nominal quadrature signals are created for each phase A, B, and C with ± 120° phase difference with each phase. I and Q signals produced by the multiplication are filtered using averaging filters. The voltage magnitude is obtained from equation (1):
V=√(I^2+Q^2 ) (1)
The phase is obtained from equation (2):
Phase=atan⁡(I/Q) (2)
. The square root and inverse function to calculate voltage and phase are achieved in FPGA using interpolation. The calculated voltage magnitude and phase are filtered with IIR filter to attenuate the 2nd order harmonic and above. To get the accurate voltage magnitude, voltage correction is implemented due to the Sinc function of the rectangular filter. The frequency value of the phasor is calculated by doing a differentiation of the phase value. The RoCoF is calculated by differentiation of the calculated frequency. The values of Voltage, Frequency, RoCoF, and timestamp are displayed on Labview.
== IQ Demodulation ==
[[File:Quarter.png|thumb]]
To obtain real and imaginary information of the phasor the input waveform needs to be down-convert
ed. The IQ down-conversion will utilise quadrature signals that generated from the previous sections. The process of IQ down-conversion will cause the signals to be in the baseband region.

The digitised 16 bits input from the ADC is multiplied with quadrature signals generated from the LuT. The multiplication process utilises the 18-bit x 18-bit embedded multiplier inside the MAX10. Although there many multiplication algorithms that can be implemented such as Booth multiplication algorithms, using the embedded multiplier prove to be the easiest to implement. The embedded multipliers take account the signed integer during the multiplication process. There no need for an extra algorithm to sort the signed bits for the multiplication.

== IIR Filter ==
[[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

This topic presents the development of the IIR filter towards the implementation of FPGA.
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power
systems. This section shows the VHDL routines designed in the Quartus Prime software
based on the MATLAB algorithm. VHDL is a hardware description language used to
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point
standard. The operations are carried on mantissa, exponents, and sign components. This
includes the routine to convert the filter coefficients from the algorithms in a signed
floating-point format.

=== Literature Review ===
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the
voltage and current analog inputs before the computation begins. Ref [8] reports that
their PMU design is using the window method of FIR filter. The performance of the filter
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main
frequency

== Method ==

=== Implementation of IIR Filter ===
[[File:Single Precision IEEE 754 Floating-Point Standard.png|300px|frame|centre|Single Precision IEEE 754 Floating-Point Standard]]
 
==== Floating point addition operation ====

The addition operation is performed based on the steps as follows:

1. Smaller exponent number is rewritten to match with the larger exponent number.
 
2. Adding of the mantissas.
 
3. Normalise the sum and checking process for the underflow and overflow.
 
4. Rounding the sum.

The state machine of the addition operation is explained here. The operation is halted and
wait for the request signal goes high. If the signal is true, the input will enter exponent
alignment process. The exponents of both input signals are set as unsigned
std_logic_vector to make the comparison. The mantissa that having smaller exponent
value will be downshifted based on the different value of the comparison. To do the
comparison, the unsigned exponent value is converted to signed value. Then, the
downshifting of the mantissa is done in integer form of the exponent different.
In normalisation process, the overflow sum is downshifted by dropping the least
significant bit.

 
==== Floating point multiplication operation ====

The multiplication operation is performed based on the steps as follows:

1. The addition of exponents to find new exponent. The biased exponents are added
twice and need to subtract it once afterward to compensate.
 
2. The multiplication of mantissas.
 
3. Normalise the product.14
 
4. Round the result.

The operation starts when the request input signal goes high. The inputs are loaded and
are multiplied with each other. Then, the normalisation process is done. Here, the
overflow of the product is checked. The result will in the form of sign, exponent, and
mantissa.

=== Establishing FPGA Communication to host PC ===
[[File:FPGA to PC block diagram.png|300px|frame|center|FPGA to PC block diagram]]
 
The FPGA communication to host PC is established by using JTAG to Avalon MM Bridge
embedded IP core provided in Quartus Prime Lite. The block diagram shown in Figure
is the design approach that is used to establish the communication link between the DE10
board and the host PC. The design required the Altera serial JTAG cable (USB-Blaster)
connected between the JTAG port on the board and a host computer running the Quartus
Prime Programmer for the duration of the hardware duration period.

[[File:Platform Designer.png|300px|thumb|centre|Platform Designer]]
The first step is to create the hardware part of the block diagram. The block diagram
shown in Figure aboce can be instantiated in Platform Designer (Quartus Prime Menu > Tools
> Platform Designer). Figure here shows a complete structure of the big block in Figure above designed
in the Platform Designer. Noted that, JTAG to Avalon Master Bridge is the only master and
other peripherals are the slaves. By assigning the unique base addresses for each of the
components, the interaction between them can simply be done by calling the specific
address of the peripheral and the master component can read or write the instruction.
The read and write are done in System Console or Tcl script.

=== Global Positioning System ===

Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.
Frequency Lock Loop(FLL): Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC.
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured from the BNC connector, therefore a division of 2 algorithm will be performed.

== Results ==
=== LabView Data Display ===
[[File:LabView Interface.png|thumb]]

=== FLL Results ===

The result of 10 mhzs generation is shown below
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]

The result of DAC sawtooth waveform is shown below
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]

The result of the FLL is shown below
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]

The result of the time/date stamp are displayed below
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]

== Conclusion ==
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

File:LabView Interface.png

2020-06-09T01:06:43Z

A1757608:

LabView interface with FPGA to view Voltage, Phase , Frequency, RoCoF

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2020-06-09T01:04:02Z

A1757608:

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
== Introduction ==

Phasor Measurement Units (PMUs) are used by the power industry to measure Voltage, Phase, Frequency and Rate of Change of Frequency (RoCoF) of the power system. The IEEE standard requires these measurements to be available within 2 mains cycles (40 mS) of the waveform sampling time. These PMU’s are an integral part of keeping the power system stable by controlling circuit breakers and generator settings in a high level of renewable power supply grid. Implementing the PMU algorithm in an FPGA is required to ensure the speed of operation and reliability required for this critical instrumentation.During 2018, Dr. Kikkert used Matlab to develop an algorithm to perform the PMU calculations quicker and with better accuracy than is possible at present. Hardware to digitise the 3 phase mains voltages has just been completed by Thesis students. This project aims to implement the floating point Matlab algorithm as a fixed point algorithm on a DE10-Lite FPGA development board from Terasic, using VHDL or Verilog. The code to be produced is to read the data from the digital to analogue converters on the existing hardware, calculate the Voltage, Phase, Frequency and RoCoF and send this data to a computer to be displayed using existing Labview code.As a second priority task, for higher grades, the same FPGA board is to be used with an available GPS receiver and existing hardware to produce a GPS time stamp for the Voltage, Phase, Frequency and RoCoF data.

=== Project Group 25601 ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* Junwen Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar

==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Dr. Said Al-Sarawi

=== Objectives ===
This project aims to achieve goals as follow:

1. To produce a fully working Phasor Measurement Unit.
2. Implement floating point Matlab algorithm in FPGA.
3. Calculate Voltage ,Phase , Frequency and RoCoF with a GPS time stamp.
4. Meet the requirement of IEEE/IEC standards.

== Background ==
Project Overview
[[File: Overview of the project.png|thumb|Project Overview]]
Three-phase 50 Hz waveforms are applied to the analogue input of the hardware circuit that was designed by Kikkert. The hardware includes a 6 channel ADC chip with 16 bits accuracy. The waveforms are sampled by the ADC chip at 10 kHz sampling rate for a 50 Hz main and can be changed to 60 Hz mains. The frequency lock loop circuit that synchronized with the GPS provides accurate sampling frequency for the ADC. The waveforms sampled by the ADC chip are digitised as 16 bits twos-complement.
Digitised waveforms are shifted to the baseband signal by multiplying with the 50 Hz quadrature signal (Cosine and Sine) that generated by the oscillator which is synchronized with the GPS. The quadrature signals are digitally synthesized by Lookup Table (LuT). The nominal quadrature signals are created for each phase A, B, and C with ± 120° phase difference with each phase. I and Q signals produced by the multiplication are filtered using averaging filters. The voltage magnitude is obtained from equation (1):
V=√(I^2+Q^2 ) (1)
The phase is obtained from equation (2):
Phase=atan⁡(I/Q) (2)
. The square root and inverse function to calculate voltage and phase are achieved in FPGA using interpolation. The calculated voltage magnitude and phase are filtered with IIR filter to attenuate the 2nd order harmonic and above. To get the accurate voltage magnitude, voltage correction is implemented due to the Sinc function of the rectangular filter. The frequency value of the phasor is calculated by doing a differentiation of the phase value. The RoCoF is calculated by differentiation of the calculated frequency. The values of Voltage, Frequency, RoCoF, and timestamp are displayed on Labview.
== IQ Demodulation ==
[[File:Quarter.png|thumb]]
To obtain real and imaginary information of the phasor the input waveform needs to be down-convert
ed. The IQ down-conversion will utilise quadrature signals that generated from the previous sections. The process of IQ down-conversion will cause the signals to be in the baseband region.

The digitised 16 bits input from the ADC is multiplied with quadrature signals generated from the LuT. The multiplication process utilises the 18-bit x 18-bit embedded multiplier inside the MAX10. Although there many multiplication algorithms that can be implemented such as Booth multiplication algorithms, using the embedded multiplier prove to be the easiest to implement. The embedded multipliers take account the signed integer during the multiplication process. There no need for an extra algorithm to sort the signed bits for the multiplication.

== IIR Filter ==
[[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

This topic presents the development of the IIR filter towards the implementation of FPGA.
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power
systems. This section shows the VHDL routines designed in the Quartus Prime software
based on the MATLAB algorithm. VHDL is a hardware description language used to
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point
standard. The operations are carried on mantissa, exponents, and sign components. This
includes the routine to convert the filter coefficients from the algorithms in a signed
floating-point format.

=== Literature Review ===
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the
voltage and current analog inputs before the computation begins. Ref [8] reports that
their PMU design is using the window method of FIR filter. The performance of the filter
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main
frequency

== Method ==

=== Implementation of IIR Filter ===
[[File:Single Precision IEEE 754 Floating-Point Standard.png|300px|frame|centre|Single Precision IEEE 754 Floating-Point Standard]]
 
==== Floating point addition operation ====

The addition operation is performed based on the steps as follows:

1. Smaller exponent number is rewritten to match with the larger exponent number.
 
2. Adding of the mantissas.
 
3. Normalise the sum and checking process for the underflow and overflow.
 
4. Rounding the sum.

The state machine of the addition operation is explained here. The operation is halted and
wait for the request signal goes high. If the signal is true, the input will enter exponent
alignment process. The exponents of both input signals are set as unsigned
std_logic_vector to make the comparison. The mantissa that having smaller exponent
value will be downshifted based on the different value of the comparison. To do the
comparison, the unsigned exponent value is converted to signed value. Then, the
downshifting of the mantissa is done in integer form of the exponent different.
In normalisation process, the overflow sum is downshifted by dropping the least
significant bit.

 
==== Floating point multiplication operation ====

The multiplication operation is performed based on the steps as follows:

1. The addition of exponents to find new exponent. The biased exponents are added
twice and need to subtract it once afterward to compensate.
 
2. The multiplication of mantissas.
 
3. Normalise the product.14
 
4. Round the result.

The operation starts when the request input signal goes high. The inputs are loaded and
are multiplied with each other. Then, the normalisation process is done. Here, the
overflow of the product is checked. The result will in the form of sign, exponent, and
mantissa.

=== Establishing FPGA Communication to host PC ===
[[File:FPGA to PC block diagram.png|300px|frame|center|FPGA to PC block diagram]]
 
The FPGA communication to host PC is established by using JTAG to Avalon MM Bridge
embedded IP core provided in Quartus Prime Lite. The block diagram shown in Figure
is the design approach that is used to establish the communication link between the DE10
board and the host PC. The design required the Altera serial JTAG cable (USB-Blaster)
connected between the JTAG port on the board and a host computer running the Quartus
Prime Programmer for the duration of the hardware duration period.

[[File:Platform Designer.png|300px|thumb|centre|Platform Designer]]
The first step is to create the hardware part of the block diagram. The block diagram
shown in Figure aboce can be instantiated in Platform Designer (Quartus Prime Menu > Tools
> Platform Designer). Figure here shows a complete structure of the big block in Figure above designed
in the Platform Designer. Noted that, JTAG to Avalon Master Bridge is the only master and
other peripherals are the slaves. By assigning the unique base addresses for each of the
components, the interaction between them can simply be done by calling the specific
address of the peripheral and the master component can read or write the instruction.
The read and write are done in System Console or Tcl script.

=== Global Positioning System ===

Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.
Frequency Lock Loop(FLL): Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC.
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured from the BNC connector, therefore a division of 2 algorithm will be performed.

== Results ==

=== FLL Results ===

The result of 10 mhzs generation is shown below
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]

The result of DAC sawtooth waveform is shown below
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]

The result of the FLL is shown below
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]

The result of the time/date stamp are displayed below
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]

== Conclusion ==
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

File:Quarter.png

2020-06-09T01:03:34Z

A1757608:

Quarter wave waveform is used in the LUT to save resource .

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2020-06-09T00:57:44Z

A1757608: /* FLL RESULTs */

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
== Introduction ==

Phasor Measurement Units (PMUs) are used by the power industry to measure Voltage, Phase, Frequency and Rate of Change of Frequency (RoCoF) of the power system. The IEEE standard requires these measurements to be available within 2 mains cycles (40 mS) of the waveform sampling time. These PMU’s are an integral part of keeping the power system stable by controlling circuit breakers and generator settings in a high level of renewable power supply grid. Implementing the PMU algorithm in an FPGA is required to ensure the speed of operation and reliability required for this critical instrumentation.During 2018, Dr. Kikkert used Matlab to develop an algorithm to perform the PMU calculations quicker and with better accuracy than is possible at present. Hardware to digitise the 3 phase mains voltages has just been completed by Thesis students. This project aims to implement the floating point Matlab algorithm as a fixed point algorithm on a DE10-Lite FPGA development board from Terasic, using VHDL or Verilog. The code to be produced is to read the data from the digital to analogue converters on the existing hardware, calculate the Voltage, Phase, Frequency and RoCoF and send this data to a computer to be displayed using existing Labview code.As a second priority task, for higher grades, the same FPGA board is to be used with an available GPS receiver and existing hardware to produce a GPS time stamp for the Voltage, Phase, Frequency and RoCoF data.

=== Project Group 25601 ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* Junwen Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar

==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Dr. Said Al-Sarawi

=== Objectives ===
This project aims to achieve goals as follow:

1. To produce a fully working Phasor Measurement Unit.
2. Implement floating point Matlab algorithm in FPGA.
3. Calculate Voltage ,Phase , Frequency and RoCoF with a GPS time stamp.
4. Meet the requirement of IEEE/IEC standards.

== Background ==
Project Overview
[[File: Overview of the project.png|thumb|Project Overview]]
Three-phase 50 Hz waveforms are applied to the analogue input of the hardware circuit that was designed by Kikkert. The hardware includes a 6 channel ADC chip with 16 bits accuracy. The waveforms are sampled by the ADC chip at 10 kHz sampling rate for a 50 Hz main and can be changed to 60 Hz mains. The frequency lock loop circuit that synchronized with the GPS provides accurate sampling frequency for the ADC. The waveforms sampled by the ADC chip are digitised as 16 bits twos-complement.
Digitised waveforms are shifted to the baseband signal by multiplying with the 50 Hz quadrature signal (Cosine and Sine) that generated by the oscillator which is synchronized with the GPS. The quadrature signals are digitally synthesized by Lookup Table (LuT). The nominal quadrature signals are created for each phase A, B, and C with ± 120° phase difference with each phase. I and Q signals produced by the multiplication are filtered using averaging filters. The voltage magnitude is obtained from equation (1):
V=√(I^2+Q^2 ) (1)
The phase is obtained from equation (2):
Phase=atan⁡(I/Q) (2)
. The square root and inverse function to calculate voltage and phase are achieved in FPGA using interpolation. The calculated voltage magnitude and phase are filtered with IIR filter to attenuate the 2nd order harmonic and above. To get the accurate voltage magnitude, voltage correction is implemented due to the Sinc function of the rectangular filter. The frequency value of the phasor is calculated by doing a differentiation of the phase value. The RoCoF is calculated by differentiation of the calculated frequency. The values of Voltage, Frequency, RoCoF, and timestamp are displayed on Labview.

== IIR Filter ==
[[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

This topic presents the development of the IIR filter towards the implementation of FPGA.
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power
systems. This section shows the VHDL routines designed in the Quartus Prime software
based on the MATLAB algorithm. VHDL is a hardware description language used to
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point
standard. The operations are carried on mantissa, exponents, and sign components. This
includes the routine to convert the filter coefficients from the algorithms in a signed
floating-point format.

=== Literature Review ===
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the
voltage and current analog inputs before the computation begins. Ref [8] reports that
their PMU design is using the window method of FIR filter. The performance of the filter
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main
frequency

== Method ==

=== Implementation of IIR Filter ===
[[File:Single Precision IEEE 754 Floating-Point Standard.png|300px|frame|centre|Single Precision IEEE 754 Floating-Point Standard]]
 
==== Floating point addition operation ====

The addition operation is performed based on the steps as follows:

1. Smaller exponent number is rewritten to match with the larger exponent number.
 
2. Adding of the mantissas.
 
3. Normalise the sum and checking process for the underflow and overflow.
 
4. Rounding the sum.

The state machine of the addition operation is explained here. The operation is halted and
wait for the request signal goes high. If the signal is true, the input will enter exponent
alignment process. The exponents of both input signals are set as unsigned
std_logic_vector to make the comparison. The mantissa that having smaller exponent
value will be downshifted based on the different value of the comparison. To do the
comparison, the unsigned exponent value is converted to signed value. Then, the
downshifting of the mantissa is done in integer form of the exponent different.
In normalisation process, the overflow sum is downshifted by dropping the least
significant bit.

 
==== Floating point multiplication operation ====

The multiplication operation is performed based on the steps as follows:

1. The addition of exponents to find new exponent. The biased exponents are added
twice and need to subtract it once afterward to compensate.
 
2. The multiplication of mantissas.
 
3. Normalise the product.14
 
4. Round the result.

The operation starts when the request input signal goes high. The inputs are loaded and
are multiplied with each other. Then, the normalisation process is done. Here, the
overflow of the product is checked. The result will in the form of sign, exponent, and
mantissa.

=== Establishing FPGA Communication to host PC ===
[[File:FPGA to PC block diagram.png|300px|frame|center|FPGA to PC block diagram]]
 
The FPGA communication to host PC is established by using JTAG to Avalon MM Bridge
embedded IP core provided in Quartus Prime Lite. The block diagram shown in Figure
is the design approach that is used to establish the communication link between the DE10
board and the host PC. The design required the Altera serial JTAG cable (USB-Blaster)
connected between the JTAG port on the board and a host computer running the Quartus
Prime Programmer for the duration of the hardware duration period.

[[File:Platform Designer.png|300px|thumb|centre|Platform Designer]]
The first step is to create the hardware part of the block diagram. The block diagram
shown in Figure aboce can be instantiated in Platform Designer (Quartus Prime Menu > Tools
> Platform Designer). Figure here shows a complete structure of the big block in Figure above designed
in the Platform Designer. Noted that, JTAG to Avalon Master Bridge is the only master and
other peripherals are the slaves. By assigning the unique base addresses for each of the
components, the interaction between them can simply be done by calling the specific
address of the peripheral and the master component can read or write the instruction.
The read and write are done in System Console or Tcl script.

=== Global Positioning System ===

Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.
Frequency Lock Loop(FLL): Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC.
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured from the BNC connector, therefore a division of 2 algorithm will be performed.

== Results ==

=== FLL Results ===

The result of 10 mhzs generation is shown below
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]

The result of DAC sawtooth waveform is shown below
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]

The result of the FLL is shown below
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]

The result of the time/date stamp are displayed below
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]

== Conclusion ==
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2020-06-09T00:57:03Z

A1757608: /* Results */

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
== Introduction ==

Phasor Measurement Units (PMUs) are used by the power industry to measure Voltage, Phase, Frequency and Rate of Change of Frequency (RoCoF) of the power system. The IEEE standard requires these measurements to be available within 2 mains cycles (40 mS) of the waveform sampling time. These PMU’s are an integral part of keeping the power system stable by controlling circuit breakers and generator settings in a high level of renewable power supply grid. Implementing the PMU algorithm in an FPGA is required to ensure the speed of operation and reliability required for this critical instrumentation.During 2018, Dr. Kikkert used Matlab to develop an algorithm to perform the PMU calculations quicker and with better accuracy than is possible at present. Hardware to digitise the 3 phase mains voltages has just been completed by Thesis students. This project aims to implement the floating point Matlab algorithm as a fixed point algorithm on a DE10-Lite FPGA development board from Terasic, using VHDL or Verilog. The code to be produced is to read the data from the digital to analogue converters on the existing hardware, calculate the Voltage, Phase, Frequency and RoCoF and send this data to a computer to be displayed using existing Labview code.As a second priority task, for higher grades, the same FPGA board is to be used with an available GPS receiver and existing hardware to produce a GPS time stamp for the Voltage, Phase, Frequency and RoCoF data.

=== Project Group 25601 ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* Junwen Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar

==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Dr. Said Al-Sarawi

=== Objectives ===
This project aims to achieve goals as follow:

1. To produce a fully working Phasor Measurement Unit.
2. Implement floating point Matlab algorithm in FPGA.
3. Calculate Voltage ,Phase , Frequency and RoCoF with a GPS time stamp.
4. Meet the requirement of IEEE/IEC standards.

== Background ==
Project Overview
[[File: Overview of the project.png|thumb|Project Overview]]
Three-phase 50 Hz waveforms are applied to the analogue input of the hardware circuit that was designed by Kikkert. The hardware includes a 6 channel ADC chip with 16 bits accuracy. The waveforms are sampled by the ADC chip at 10 kHz sampling rate for a 50 Hz main and can be changed to 60 Hz mains. The frequency lock loop circuit that synchronized with the GPS provides accurate sampling frequency for the ADC. The waveforms sampled by the ADC chip are digitised as 16 bits twos-complement.
Digitised waveforms are shifted to the baseband signal by multiplying with the 50 Hz quadrature signal (Cosine and Sine) that generated by the oscillator which is synchronized with the GPS. The quadrature signals are digitally synthesized by Lookup Table (LuT). The nominal quadrature signals are created for each phase A, B, and C with ± 120° phase difference with each phase. I and Q signals produced by the multiplication are filtered using averaging filters. The voltage magnitude is obtained from equation (1):
V=√(I^2+Q^2 ) (1)
The phase is obtained from equation (2):
Phase=atan⁡(I/Q) (2)
. The square root and inverse function to calculate voltage and phase are achieved in FPGA using interpolation. The calculated voltage magnitude and phase are filtered with IIR filter to attenuate the 2nd order harmonic and above. To get the accurate voltage magnitude, voltage correction is implemented due to the Sinc function of the rectangular filter. The frequency value of the phasor is calculated by doing a differentiation of the phase value. The RoCoF is calculated by differentiation of the calculated frequency. The values of Voltage, Frequency, RoCoF, and timestamp are displayed on Labview.

== IIR Filter ==
[[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

This topic presents the development of the IIR filter towards the implementation of FPGA.
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power
systems. This section shows the VHDL routines designed in the Quartus Prime software
based on the MATLAB algorithm. VHDL is a hardware description language used to
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point
standard. The operations are carried on mantissa, exponents, and sign components. This
includes the routine to convert the filter coefficients from the algorithms in a signed
floating-point format.

=== Literature Review ===
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the
voltage and current analog inputs before the computation begins. Ref [8] reports that
their PMU design is using the window method of FIR filter. The performance of the filter
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main
frequency

== Method ==

=== Implementation of IIR Filter ===
[[File:Single Precision IEEE 754 Floating-Point Standard.png|300px|frame|centre|Single Precision IEEE 754 Floating-Point Standard]]
 
==== Floating point addition operation ====

The addition operation is performed based on the steps as follows:

1. Smaller exponent number is rewritten to match with the larger exponent number.
 
2. Adding of the mantissas.
 
3. Normalise the sum and checking process for the underflow and overflow.
 
4. Rounding the sum.

The state machine of the addition operation is explained here. The operation is halted and
wait for the request signal goes high. If the signal is true, the input will enter exponent
alignment process. The exponents of both input signals are set as unsigned
std_logic_vector to make the comparison. The mantissa that having smaller exponent
value will be downshifted based on the different value of the comparison. To do the
comparison, the unsigned exponent value is converted to signed value. Then, the
downshifting of the mantissa is done in integer form of the exponent different.
In normalisation process, the overflow sum is downshifted by dropping the least
significant bit.

 
==== Floating point multiplication operation ====

The multiplication operation is performed based on the steps as follows:

1. The addition of exponents to find new exponent. The biased exponents are added
twice and need to subtract it once afterward to compensate.
 
2. The multiplication of mantissas.
 
3. Normalise the product.14
 
4. Round the result.

The operation starts when the request input signal goes high. The inputs are loaded and
are multiplied with each other. Then, the normalisation process is done. Here, the
overflow of the product is checked. The result will in the form of sign, exponent, and
mantissa.

=== Establishing FPGA Communication to host PC ===
[[File:FPGA to PC block diagram.png|300px|frame|center|FPGA to PC block diagram]]
 
The FPGA communication to host PC is established by using JTAG to Avalon MM Bridge
embedded IP core provided in Quartus Prime Lite. The block diagram shown in Figure
is the design approach that is used to establish the communication link between the DE10
board and the host PC. The design required the Altera serial JTAG cable (USB-Blaster)
connected between the JTAG port on the board and a host computer running the Quartus
Prime Programmer for the duration of the hardware duration period.

[[File:Platform Designer.png|300px|thumb|centre|Platform Designer]]
The first step is to create the hardware part of the block diagram. The block diagram
shown in Figure aboce can be instantiated in Platform Designer (Quartus Prime Menu > Tools
> Platform Designer). Figure here shows a complete structure of the big block in Figure above designed
in the Platform Designer. Noted that, JTAG to Avalon Master Bridge is the only master and
other peripherals are the slaves. By assigning the unique base addresses for each of the
components, the interaction between them can simply be done by calling the specific
address of the peripheral and the master component can read or write the instruction.
The read and write are done in System Console or Tcl script.

=== Global Positioning System ===

Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.
Frequency Lock Loop(FLL): Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC.
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured from the BNC connector, therefore a division of 2 algorithm will be performed.

== Results ==
== FLL RESULTs ==
The result of 10 mhzs generation is shown below
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]

The result of DAC sawtooth waveform is shown below
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]

The result of the FLL is shown below
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]

The result of the time/date stamp are displayed below
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]

== Conclusion ==
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2020-06-09T00:55:10Z

A1757608: /* Background */

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
== Introduction ==

Phasor Measurement Units (PMUs) are used by the power industry to measure Voltage, Phase, Frequency and Rate of Change of Frequency (RoCoF) of the power system. The IEEE standard requires these measurements to be available within 2 mains cycles (40 mS) of the waveform sampling time. These PMU’s are an integral part of keeping the power system stable by controlling circuit breakers and generator settings in a high level of renewable power supply grid. Implementing the PMU algorithm in an FPGA is required to ensure the speed of operation and reliability required for this critical instrumentation.During 2018, Dr. Kikkert used Matlab to develop an algorithm to perform the PMU calculations quicker and with better accuracy than is possible at present. Hardware to digitise the 3 phase mains voltages has just been completed by Thesis students. This project aims to implement the floating point Matlab algorithm as a fixed point algorithm on a DE10-Lite FPGA development board from Terasic, using VHDL or Verilog. The code to be produced is to read the data from the digital to analogue converters on the existing hardware, calculate the Voltage, Phase, Frequency and RoCoF and send this data to a computer to be displayed using existing Labview code.As a second priority task, for higher grades, the same FPGA board is to be used with an available GPS receiver and existing hardware to produce a GPS time stamp for the Voltage, Phase, Frequency and RoCoF data.

=== Project Group 25601 ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* Junwen Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar

==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Dr. Said Al-Sarawi

=== Objectives ===
This project aims to achieve goals as follow:

1. To produce a fully working Phasor Measurement Unit.
2. Implement floating point Matlab algorithm in FPGA.
3. Calculate Voltage ,Phase , Frequency and RoCoF with a GPS time stamp.
4. Meet the requirement of IEEE/IEC standards.

== Background ==
Project Overview
[[File: Overview of the project.png|thumb|Project Overview]]
Three-phase 50 Hz waveforms are applied to the analogue input of the hardware circuit that was designed by Kikkert. The hardware includes a 6 channel ADC chip with 16 bits accuracy. The waveforms are sampled by the ADC chip at 10 kHz sampling rate for a 50 Hz main and can be changed to 60 Hz mains. The frequency lock loop circuit that synchronized with the GPS provides accurate sampling frequency for the ADC. The waveforms sampled by the ADC chip are digitised as 16 bits twos-complement.
Digitised waveforms are shifted to the baseband signal by multiplying with the 50 Hz quadrature signal (Cosine and Sine) that generated by the oscillator which is synchronized with the GPS. The quadrature signals are digitally synthesized by Lookup Table (LuT). The nominal quadrature signals are created for each phase A, B, and C with ± 120° phase difference with each phase. I and Q signals produced by the multiplication are filtered using averaging filters. The voltage magnitude is obtained from equation (1):
V=√(I^2+Q^2 ) (1)
The phase is obtained from equation (2):
Phase=atan⁡(I/Q) (2)
. The square root and inverse function to calculate voltage and phase are achieved in FPGA using interpolation. The calculated voltage magnitude and phase are filtered with IIR filter to attenuate the 2nd order harmonic and above. To get the accurate voltage magnitude, voltage correction is implemented due to the Sinc function of the rectangular filter. The frequency value of the phasor is calculated by doing a differentiation of the phase value. The RoCoF is calculated by differentiation of the calculated frequency. The values of Voltage, Frequency, RoCoF, and timestamp are displayed on Labview.

== IIR Filter ==
[[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

This topic presents the development of the IIR filter towards the implementation of FPGA.
The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited
to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer
resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE
standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power
systems. This section shows the VHDL routines designed in the Quartus Prime software
based on the MATLAB algorithm. VHDL is a hardware description language used to
program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point
standard. The operations are carried on mantissa, exponents, and sign components. This
includes the routine to convert the filter coefficients from the algorithms in a signed
floating-point format.

=== Literature Review ===
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref
[7] designing a virtual PMU to interact with the real-time simulators as a way emulating
the large number of real-life PMUs. They used the anti-aliasing filter to filter out the
voltage and current analog inputs before the computation begins. Ref [8] reports that
their PMU design is using the window method of FIR filter. The performance of the filter
is investigated based on out of band rejection, noise, and harmonic elimination. The sixth
order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main
frequency

== Method ==

=== Implementation of IIR Filter ===
[[File:Single Precision IEEE 754 Floating-Point Standard.png|300px|frame|centre|Single Precision IEEE 754 Floating-Point Standard]]
 
==== Floating point addition operation ====

The addition operation is performed based on the steps as follows:

1. Smaller exponent number is rewritten to match with the larger exponent number.
 
2. Adding of the mantissas.
 
3. Normalise the sum and checking process for the underflow and overflow.
 
4. Rounding the sum.

The state machine of the addition operation is explained here. The operation is halted and
wait for the request signal goes high. If the signal is true, the input will enter exponent
alignment process. The exponents of both input signals are set as unsigned
std_logic_vector to make the comparison. The mantissa that having smaller exponent
value will be downshifted based on the different value of the comparison. To do the
comparison, the unsigned exponent value is converted to signed value. Then, the
downshifting of the mantissa is done in integer form of the exponent different.
In normalisation process, the overflow sum is downshifted by dropping the least
significant bit.

 
==== Floating point multiplication operation ====

The multiplication operation is performed based on the steps as follows:

1. The addition of exponents to find new exponent. The biased exponents are added
twice and need to subtract it once afterward to compensate.
 
2. The multiplication of mantissas.
 
3. Normalise the product.14
 
4. Round the result.

The operation starts when the request input signal goes high. The inputs are loaded and
are multiplied with each other. Then, the normalisation process is done. Here, the
overflow of the product is checked. The result will in the form of sign, exponent, and
mantissa.

=== Establishing FPGA Communication to host PC ===
[[File:FPGA to PC block diagram.png|300px|frame|center|FPGA to PC block diagram]]
 
The FPGA communication to host PC is established by using JTAG to Avalon MM Bridge
embedded IP core provided in Quartus Prime Lite. The block diagram shown in Figure
is the design approach that is used to establish the communication link between the DE10
board and the host PC. The design required the Altera serial JTAG cable (USB-Blaster)
connected between the JTAG port on the board and a host computer running the Quartus
Prime Programmer for the duration of the hardware duration period.

[[File:Platform Designer.png|300px|thumb|centre|Platform Designer]]
The first step is to create the hardware part of the block diagram. The block diagram
shown in Figure aboce can be instantiated in Platform Designer (Quartus Prime Menu > Tools
> Platform Designer). Figure here shows a complete structure of the big block in Figure above designed
in the Platform Designer. Noted that, JTAG to Avalon Master Bridge is the only master and
other peripherals are the slaves. By assigning the unique base addresses for each of the
components, the interaction between them can simply be done by calling the specific
address of the peripheral and the master component can read or write the instruction.
The read and write are done in System Console or Tcl script.

=== Global Positioning System ===

Timestamp:The timestamp is the process of displaying the dte and time on the hardware. Receiving a message containing a time stamp on the UART interface. Decode the received message in accordance with the NMEA-0183 protocol. Make a multiplexer to switch between the time stamp and the current date stamp. And also convert the data to code 7 of the segment indicator on the FPGA.
Frequency Lock Loop(FLL): Locking a desired frequency using PID algorithm since the PID algorithm can compare the measured value with the desired value and out in automatic control. measure the frequency of the VCXO generator. Calculate the frequency error and determine the following DAC value using the PID algorithm. Transfer data to the DAC.
10Mhz Generator: There is a 20mhz crystal control voltage oscillator on the printed circuit board, a 10mhz is required to be measured from the BNC connector, therefore a division of 2 algorithm will be performed.

== Results ==
The result of 10 mhzs generation is shown below
[[File:DDF741B8-92B4-4A21-B3EA-535069D6F1D4 4 5005 c.jpg|thumb]]

The result of DAC sawtooth waveform is shown below
[[File:91F904F0-21DA-48C4-B0B2-073DC2BF7505 4 5005 c.jpg|thumb]]

The result of the FLL is shown below
[[File:62668430-3528-4145-BCD4-E46A3716EDE8.jpg|thumb]]

The result of the time/date stamp are displayed below
[[File:0C129181-DEFC-44F4-86E1-E55D648C6D7F 4 5005 c.jpg|thumb]]

== Conclusion ==
The DAC sawtooth waveform, 10 Mhz desired frequency generation and the time/date stamp have been successfully achieved, however, the frequency lock loop was not locking for the 20 Mhz due to the harmonics interference. A smaller capacitor should be considered for C80 since C83 is 100 time bigger then the DAC waveform could be smoothed out and the triangular waveform could not be observe when the jumper is on pin 2 and 3 of JP1

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

File:Overview of the project.png

2020-06-09T00:53:52Z

A1757608:

The project consists of multiple-stages which are IQ modulation, Averaging Filter, Phase and Voltage Calculation and IIR filter and lastly communication to computer

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2019-09-21T11:44:19Z

A1757608:

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2019-09-19T10:01:40Z

A1757608:

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Abstract to be added
== Introduction ==
Project description here

=== Project team ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* JunWeng Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar
==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Said Al-Sarawi

==== Advisors ====
*
*

=== Objectives ===
Set of objectives
To Implement floating-point algorithm as fixed-point algorithm in FPGA

== Background ==
=== Topic 1 ===

== Method ==

== Results ==

== Conclusion ==

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2019-09-19T10:00:30Z

A1757608: /* Objectives */

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Abstract here
== Introduction ==
Project description here

=== Project team ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* JunWeng Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar
==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Said Al-Sarawi

==== Advisors ====
*
*

=== Objectives ===
Set of objectives
To Implement floating-point algorithm as fixed-point algorithm in FPGA

== Background ==
=== Topic 1 ===

== Method ==

== Results ==

== Conclusion ==

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.

Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation

2019-09-19T09:59:35Z

A1757608: Created page with "Category:Projects Category:Final Year Projects 106 Abstract here == Introduction == Project description here === Project team === ==== Project stu..."

[[Category:Projects]]
[[Category:Final Year Projects]]
[[Category:2018s1|106]]
Abstract here
== Introduction ==
Project description here

=== Project team ===
==== Project students ====
* Rui Yang
* Mohamad Hafiz Mohamad Rodzi
* JunWeng Zheng
* Sayed Mohd Amir Shahirudin Sayed Sagar
==== Supervisors ====
* A/Prof. Cornelis Keith Kikkert
* Said Al-Sarawi

==== Advisors ====
*
*

=== Objectives ===
Set of objectives

== Background ==
=== Topic 1 ===

== Method ==

== Results ==

== Conclusion ==

== References ==
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.