Projects:2017s1-111 OTHR Alternative Computing Architecture - Revision history

A1646441: /* Supervisors */

2017-10-29T07:09:19Z

‎Supervisors

A1646441: /* Future Work */

2017-10-29T07:08:55Z

‎Future Work

A1646441: Future Work 1 of 2

2017-10-29T07:05:08Z

Future Work 1 of 2

A1646441: /* Lessons Learnt */

2017-10-29T06:53:18Z

‎Lessons Learnt

A1646441: /* Lessons Learnt */

2017-10-29T06:52:31Z

‎Lessons Learnt

A1646441: /* FPGA Experimentation */

2017-10-29T06:35:17Z

‎FPGA Experimentation

A1646441: General Case Mapping Insights Images

2017-10-29T06:34:04Z

General Case Mapping Insights Images

A1646441: General Case Mapping Insights 2 of 2

2017-10-29T06:30:07Z

General Case Mapping Insights 2 of 2

A1646441: General Case Mapping Insights 1 of 2

2017-10-29T06:16:07Z

General Case Mapping Insights 1 of 2

A1646441: /* Comparison of Final Architectures */

2017-10-29T05:47:43Z

‎Comparison of Final Architectures

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 == Supervisors ==
 Dr Braden Phillips<br>
-Mr Shane Breandler BAE Systems (External)
+BAE Systems Australia (External)
 == Abstract ==

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 <br>
 '''Full System Test'''<br>
 <br>
 '''High Level Synthesis'''<br>

← Older revision		Revision as of 07:05, 29 October 2017
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	== Future Work ==		== Future Work ==
		+	'''Addition of New Architectures'''<br>
		+	The choice of architectures used in this project was limited by availability and thus we were not able to use the latest and best of each technology. In the duration of the project new architectures for both GPU and CPU were either announced or released. Thus a range of new architectures could be used in a future version of this project. These include:
		+	NVIDIA Volta: The newest architecture that NVIDIA intends to release in 2018 is the first GPU to make use of TensorCores. TensorCores are
		+	NVIDIA's implementation of a processor designed for big data and machine learning applications including Google search and
		+	translate to accelerate neural network computation.
		+	AMD Ryzen and Intel i9: AMD and Intel have both released their newest CPU architectures with ever increasing number of cores. These
		+	both could be potential areas of look into.
		+	Other GPU Cards: both the use of AMD graphics cards, OpenCL and the Vulkan GPU architecture could all be areas of interest in GPU domain.
		+	Other Architectures: numerous architectures that were not considered could be investigated including non Xilinx FPGA devices, Raspberry
		+	PI and even Mobile Graphics.
		+
		+	<br>
		+	'''Role of Hardware'''<br>
		+	Budget restrictions played a major role in the scope of this project and as such simulation of hardware was preferred over testing on real devices such as fabricating an ASIC or programming an FPGA. Thus using the projects results, the most viable architectures could be expanded into a range of physical hardware options allowing factors that were not identified during simulations such as noise and the effect of the environment. This would give a better overview of each architectures strengths allowing for more accurate recommendations.
		+
		+	<br>
		+	'''Full System Test'''<br>
		+
		+	<br>
		+	'''High Level Synthesis'''<br>

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 == Lessons Learnt ==
 '''Tools and System'''<br>
 One of the major problems found during the project was acquiring a concise set of tools that were able to handle all aspects of the project. Due to restrictions on licensing some of the choices were limited and thus could not be changed, with others chosen based on research. Some tools such as the CUDA programs were run

← Older revision		Revision as of 06:52, 29 October 2017
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	== Lessons Learnt ==		== Lessons Learnt ==
		+	<br>
		+	'''Tools and System'''<br>
		+	One of the major problems found during the project was acquiring a concise set of tools that were able to handle all aspects of the project. Due to restrictions on licensing some of the choices were limited and thus could not be changed, with others chosen based on research. Some tools such as the CUDA programs were run
		+	on Windows to have access to the GPU, whilst others such as PGI were only runnable on Linux. This meant that a Virtual machine was needed to ensure the tools ran on the same CPU but likely affected the results. This restriction also limited the use of the supercomputers. Upgrading the supercomputer to utilise the latest tools and to record all metrics could have allowed for more varied results.
		+
		+	<br>
		+	'''Control and Hardware'''<br>
		+	A large number of programs were used in the project across multiple systems. Over the duration of the project some of these systems underwent upgrades changing parts of the hardware such that the initial results using the reference equation may have slightly different specification than the final algorithm. This meant that the results were not as accurate as they otherwise could have been if a single machine was used that contained all CPU and GPU devices and was not modified over the duration of the project.
		+
		+	<br>
		+	'''Focus on Scope'''<br>
		+	When the project first began, the scope specified the use of a single algorithm to compared the four architectures. However due to delays and the complexity
		+	that would be introduced by such an algorithm, the scope of the project was changed to allow an initial investigatory algorithm. This reference equation focused on the tools and developed insight into the general case of mapping architectures. This came at the reduction of time spent on the final comparisons. Thus finding a balance between exploration and comparison would have lead to a more balanced project.

	== Future Work ==		== Future Work ==

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 [[File:FPGA Devices.JPG]]
-. Even when using a small algorithm with less than 500 lines of code, synthesis targets were not met by all devices. The two cheapest available models, the series 7 Spartan and Artix both provided fewer `Digital Signal Processing blocks' than needed for synthesis.
+. Even when using a small algorithm with less than 500 lines of code, synthesis targets were not met by all devices.
 . The Spartan 7 was the only device unable to reach the timing constraint of 10 ns.
 . Each device produced a slightly different estimated clock despite having the same target constraint

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 <br>
 '''Parallel Programming and Race Conditions'''<br>
 As found that parallellising an algorithm without first considering the effect it will have on any critical sections can lead to incorrect results. When using compiler directive to parallelise a file-write loop it was found that the algorithm would produce incorrect formatting into the text file such that the output was unreadable.  Although the function to compute the arrays was performed correctly in a single thread, the output file was written in multiple threads which could run at the same time. Due to race conditions the order in which output text was written was
 not preserved or guaranteed to complete before the next thread tries to write leading to the jumbled order.
 Additionally when parallelising multiple runs of the same program with each thread using the same memory locations for the array. Hence although each run through the program could occur in its own thread, all threads shared the same memory thus the array would be comprised of data from all four cores at any one time. The text file was written in the correct format as it occurred in after the threads converged, plots were produced that show the incorrect output.
 <br>

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 <br>
 '''Recursion and Other Architectures'''<br>
 <br>
 '''Use of Language Techniques'''<br>
 == Lessons Learnt ==
 == Future Work ==

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 As gaining accurate power measurements of a single component of a larger computer system was not possible with the tools available, power measurements were based on manufacturer recommendations. The summary of power measurements show that the FPGA and CPU consume similar amounts of power whilst the GPU is considerably more power intensive leading to increased running costs.
 <br>
 '''Cost Considerations'''<br>
 As each generation of architecture is constantly being updated and released, accurate cost measurements were hard to acquire with new models released across the duration of the project. When considering the relative differences in cost, the price of the GPU and FPGA were similar with CPU costing about half the price of the others. However it is likely that both the GPU and FPGA would act as a co-processor and thus still requires a CPU to run further increasing the cost of these architectures.