Projects:2017s1-122 On-Chip Learning - Revision history

A1680892: /* References */

2017-10-28T09:19:59Z

‎References

A1680892 at 09:18, 28 October 2017

2017-10-28T09:18:52Z

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A1681557 at 10:43, 21 September 2017

2017-09-21T10:43:20Z

A1681557 at 10:40, 21 September 2017

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A1681557: /* Group members */

2017-09-21T10:39:20Z

‎Group members

A1681557: /* Group members */

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‎Group members

A1681557 at 10:38, 21 September 2017

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A1067065 at 06:06, 21 September 2017

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A1680892 at 03:26, 14 September 2017

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A1680892: Created page with "On-chip Learning"

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Created page with "On-chip Learning"

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On-chip Learning

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 [1] N. Hemsoth (2016), FPGA BASED DEEP LEARNING ACCELERATORS TAKE ON ASICS [Online]. Available: https://www.nextplatform.com/2016/08/23/fpga-based-deep-learning-accelerators-take-asics/
 [2] A. Dubious, “It’s in the Numbers Baby,” Transaction on Everything 9, no.4, pp.42-749, 1984.
 [3] M. Shagger, Reflexive Perspectives on Post-Modern Verbosity, 3rd ed. Addison-Hall, 1968.
 [4] A. Turing, “COMPUTING MACHINERY AND INTELLIGENCE,” MIND. 59.236, pp. 433-460, Oct.1950.
 [5] C. Robert, “A brief history of machine learning,” Slide share, Jun.2016.
 [6] M. A. Nielsen, “Using neural nets to recognize handwritten digits,” in Neural Networks and Deep Learning. Determination Press, 2015.
 [7] T. Yaniv, Y. Ming, R. Marc’Aurelion, W. Lior, “DeepFace: Closing the Gap to Human-Level Performance in Face Verification,” in Conference on Computer Vision and Pattern Recognition, Jun. 2014.
 [8] G. E. Hinton, “Learning multiple layers of representation,” Trends in Cognitive Science, 11, pp. 428-434, 2007.
 [9] A. Krizhevsky, “ImageNet Classification with Deep Convolution Neural Networks,” Advances in Neural Information Processing Systems 25, 2012.
 [10] Y. Benign, “Learning Deep Architectures for AI[J],” in Foundations & Trends in Machine Learning, 2(1), pp. 1-127, 2009.
   [11] W. Remigiusz, “Synthesis of compositional microprogram control units for programmable devices,” University of Zielona Góra, Zielona Góra, pp. 153, 2009.
 [12] S. Higginbotham (2016), GOOGLE TAKES UNCONVENTIONAL ROUTE WITH HOMEGROWN MACHINE LEARNING CHIPS [Online]. Available: https://www.nextplatorm.com/2016/05/19/google-takes-unconventional-routehomegr own-machine-learning-chips/
-[13] DeePHi. (2017). Investors [Online]. Available: http://www.deephi.com/index.html#contac t
 [14] J. Park, W. Sung, “FPGA BASED IMPLEMENTATION OF DEEP NEURAL NETWORKS USING ON-CHIP MEMORY ONLY,” Department of Electrical and Computer Engineering, Seoul National University, Korea, Aug. 2016.
 [15] M. Rastegari, V. Ordonez, J. Redmon, A. Farhadi, “XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks,” Allen Institute for AI, University of Washington, Aug. 2016.
 [16] F. Li et al., “Ternary weight networks,” 30th Conference om Neural Information Processing System, Barcelona, Spain, 2016.
 [17] M. Panicker and C. Babu, “Efficient FPGA Implementation of Sigmoid and Bipolar Sigmoid Activation Functions for Multilayer Perceptrons,” IOSR Journal of Engineering, vol.2, no. 6, pp. 1352-1356, June, 2012.
 [18] Girau, B, “FPNA: CONCEPTS AND PROPERTIES,” FPGA Implementations of Neural Networks, 2006, pp.63-102.
 [19] C. Z. Tang and H. K. Kwan, “Multiplayer Feedforward Neural Networks with Single Power-of-two Weights,” IEEE TRANSACTIONS ON SIGNAL PROCESSING, August, 1993, pp.2724-2727.

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 = Supervisor =
-Dr Braden Phillips
+Dr Braden Phillips,
 George Stamatescu

@@ Line 1: / Line 1: @@
 = Supervisor =
 Dr Braden Phillips
 = Group members =

@@ Line 4: / Line 4: @@
 = Group members =
 Xiaoyang Dai
-/n Tao Zeng
+, Tao Zeng
 = Abstract =

@@ Line 4: / Line 4: @@
 = Group members =
 Xiaoyang Dai
-Tao Zeng
+/n Tao Zeng
 = Abstract =

← Older revision		Revision as of 10:38, 21 September 2017
Line 1:		Line 1:
		+	= Supervisor =
		+	Dr Braden Phillips
		+
		+	= Group members =
		+	Xiaoyang Dai
		+	Tao Zeng

	= Abstract =		= Abstract =

@@ Line 1: / Line 1: @@
-Abstract
+= Abstract =
 This thesis explores efficient methods to implement a digit classification neural network on a chip. Various approaches are evaluated. Following the score of this study, comprehensive comparison and evaluation are made among a group of available weight quantization methods, power-of-two and normalized power-of-two quantization are determined as two first-rate quantization approaches. Further, three network optimization strategies including neuron replacement, alternative activation functions and matrix multiplication optimization are raised and tested in this thesis to make the target neural network more hardware friendly and simplify the hardware implementation. The present results are essential components of the proposed outcomes and indicate the future steps of this study.
-Introduction
+= Introduction =
 Deep learning neural networks is becoming popular and being widely researched in a large range of areas because of its magnificent performance, strong adaptability and bright commercial prospect. However, as a result of deep learning neural networks’ strict requirements to hardware platforms and energy support, so far, the applications of neural networks in the areas which have restrictions in hardware resource and energy consumption such as the Internet of things are limited. Consequently, the efficient and commercial implementations of neural networks are in high demand[1]. In this thesis, Field-Programmable Gate Array (FPGA) based implementations of a digit classification deep neural network is researched with focusing on the necessary weight quantization strategies and the network optimizations for FPGA.

← Older revision		Revision as of 03:26, 14 September 2017
Line 1:		Line 1:
	On-chip Learning		On-chip Learning
		+
		+	Abstract
		+
		+	This thesis explores efficient methods to implement a digit classification neural network on a chip. Various approaches are evaluated. Following the score of this study, comprehensive comparison and evaluation are made among a group of available weight quantization methods, power-of-two and normalized power-of-two quantization are determined as two first-rate quantization approaches. Further, three network optimization strategies including neuron replacement, alternative activation functions and matrix multiplication optimization are raised and tested in this thesis to make the target neural network more hardware friendly and simplify the hardware implementation. The present results are essential components of the proposed outcomes and indicate the future steps of this study.
		+
		+	Introduction
		+
		+	Deep learning neural networks is becoming popular and being widely researched in a large range of areas because of its magnificent performance, strong adaptability and bright commercial prospect. However, as a result of deep learning neural networks’ strict requirements to hardware platforms and energy support, so far, the applications of neural networks in the areas which have restrictions in hardware resource and energy consumption such as the Internet of things are limited. Consequently, the efficient and commercial implementations of neural networks are in high demand[1]. In this thesis, Field-Programmable Gate Array (FPGA) based implementations of a digit classification deep neural network is researched with focusing on the necessary weight quantization strategies and the network optimizations for FPGA.