Projects:2018s2-235UG PMU Test generator - Revision history

A1680764: /* References */

2019-06-10T06:53:00Z

‎References

A1680764: /* Testing */

2019-06-10T06:50:47Z

‎Testing

A1680764: /* Conclusion */

2019-06-10T06:43:16Z

‎Conclusion

A1680764: /* Design */

2019-06-10T06:42:55Z

‎Design

A1680764: /* Design power amplifier board */

2019-06-10T06:34:59Z

‎Design power amplifier board

A1680764: /* Design power amplifier board */

2019-06-10T06:34:34Z

‎Design power amplifier board

A1680764: /* Design DAC board */

2019-06-10T06:33:04Z

‎Design DAC board

A1680764: /* Design DAC board */

2019-06-10T06:31:43Z

‎Design DAC board

A1680764: /* Design DAC board */

2019-06-10T06:30:42Z

‎Design DAC board

A1680764: /* Design DAC board */

2019-06-10T06:29:58Z

‎Design DAC board

← Older revision		Revision as of 06:53, 10 June 2019
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	*[2] 6135A/PMUCAL Phasor Measurement Unit Calibration system. Available: https://au.flukecal.com/products/electrical-calibration/electrical-calibrators/6135apmucal-phasor-measurement-unit-calibrati?quicktabs_product_details=0		*[2] 6135A/PMUCAL Phasor Measurement Unit Calibration system. Available: https://au.flukecal.com/products/electrical-calibration/electrical-calibrators/6135apmucal-phasor-measurement-unit-calibrati?quicktabs_product_details=0
	*[3] Phasor Measurement Unit. Available: https://en.wikipedia.org/wiki/Phasor_measurement_unit		*[3] Phasor Measurement Unit. Available: https://en.wikipedia.org/wiki/Phasor_measurement_unit
		+	*[4]

← Older revision		Revision as of 06:50, 10 June 2019
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	== Testing ==		== Testing ==
		+	Before testing the whole project, make sure that each board can work appropriately so that each board can be connected and power supply can be used. The order of connection is DAC board, power amplifier board, and transformer. The power supply range of the whole project is between 12V and 26V. The DAC board needs 3V input voltage. Then the 3.3V connection point is found from the header of the DAC board and connected to the header of the power amplifier board through a small switch. The output terminal of the transformer is connected to the PC scope, by a probe (x100) and then connected to the computer.
		+
		+	After the above connection is ready, the power switch can be turned on for testing, and the following two pictures are obtained:
		+
		+
		+	The first diagram shows the relationship between the input voltage from the signal generator and the output voltage of the transformer output port. The input voltage Vrms is 709 mV and the output voltage Vrms is 236.5 V. the output voltage is within the standard output voltage range of the transformer.
		+
		+	The second figure shows the distortion of the output voltage. The picture reads total harmonics distortion at 0.215% and less than 1%, which is what we want.
		+
		+	If the voltage continues to increase, the peak and trough values of the output voltage of the first diagram will occur in the case of clipping at the same time. The distortion in the second picture will also have noise, and the THD will be close to 1%.

	== Conclusion ==		== Conclusion ==

@@ Line 92: / Line 92: @@
 The project has now succeeded in achieving most of its objectives Each part of the hardware has been tested and is working correctly.
 The group has been successful in achieving output of 276 V without saturation and THD of less than 1%.
 For the future of this project, it should be the more advanced intelligent technology in the world today. Its appearance is crucial for the dynamic network. In the future, it may involve more fields and solve more complicated problems in human life
 == References ==

@@ Line 37: / Line 37: @@
 === Project process ===
 [[File:process.PNG|thumb|The project process of PMU]]
-Project design uses regularity extensively throughout process by designing and simulating phase A only and apply the same design to phase B and C.
+Project design uses regularity extensively throughout the process by designing and simulating phase A only and apply the same design to phase B and C.
 === Approach ===
 [[File:PMU.PNG|thumb|The approach of PMU test generator]]
-The design, development and testing of PMU test generator follows system engineering approach using V model The V model process illustrate different stages of the conceptual exploration of the project verification process, implementation and validation of the system
+The design, development, and testing of PMU test generator follows system engineering approach using V model The V model process illustrate different stages of the conceptual exploration of the project verification process, implementation and validation of the system
 === Design DAC board===
@@ Line 83: / Line 83: @@
 Three LEDs placed on the board to indicate the state of the power amplifier. One of the LED is used to indicate the DC voltage presence to the board while the other two LEDs are used for error notification to the operation. at the input to enable visual inspection of the fault, over temperature and reset. During operation, all the LEDs are expected to be on indicating a healthy operation. As soon as one these turn off,
 The common one that might turn off is the fault that causes the power amplifier.
 == Testing ==

@@ Line 75: / Line 75: @@
 Power amplifier Schematic and PCB layout are in accordance with the recommended Schematic and PCB in TPA3244 datasheet [9, p.22, p.38].
-PCB has copper traces on both sides and they are showing as lines connecting terminals. As illustrated on the PCB layout in figure ##, the input (left-hand side) and the output (right-hand side) of the power amplifier copper traces have different width.
+PCB has copper traces on both sides and they are showing as lines connecting terminals. As illustrated on the PCB layout, the input (left-hand side) and the output (right-hand side) of the power amplifier copper traces have different width.
 The supply voltage decoupling capacitor is positioned close to the device per datasheet recommendation [9, Fig.23] connected directly to the device pin on the top layer. The decoupling capacitors values are also changed to 1000uF.

← Older revision		Revision as of 06:34, 10 June 2019
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	=== Design power amplifier board===		=== Design power amplifier board===
		+	Power amplifier Schematic and PCB layout are in accordance with the recommended Schematic and PCB in TPA3244 datasheet [9, p.22, p.38].
		+
		+	PCB has copper traces on both sides and they are showing as lines connecting terminals. As illustrated on the PCB layout in figure ##, the input (left-hand side) and the output (right-hand side) of the power amplifier copper traces have different width.
		+
		+	The supply voltage decoupling capacitor is positioned close to the device per datasheet recommendation [9, Fig.23] connected directly to the device pin on the top layer. The decoupling capacitors values are also changed to 1000uF.
		+
		+	Power pads placed under devices for dissipating heat generated during operation.

		+	Three LEDs placed on the board to indicate the state of the power amplifier. One of the LED is used to indicate the DC voltage presence to the board while the other two LEDs are used for error notification to the operation. at the input to enable visual inspection of the fault, over temperature and reset. During operation, all the LEDs are expected to be on indicating a healthy operation. As soon as one these turn off,
		+	The common one that might turn off is the fault that causes the power amplifier.

	== Testing ==		== Testing ==

← Older revision		Revision as of 06:33, 10 June 2019
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	Bypass capacitors are used at every DC power supply in order to minimize the noise and distortion that could contribute to the output signal.		Bypass capacitors are used at every DC power supply in order to minimize the noise and distortion that could contribute to the output signal.
		+
		+	PCB is designed to house the voltage regulators at the edge (top) of the PCB in order to enable the heatsinking.
		+
		+	The input headers are placed at the left-hand side of the board near the 40pin header connected to the FPGA while the outputs are placed at the right-hand side that can be placed next to the power amplifier board.
		+
		+	Additionally, the jumper is placed at the output of each DAC that can be used to test the analog section of the project independent of the digital signal.
		+
		+	Double layer PCB is used to enable a compact design that uses fewer spaces and reduces the manufacturing prices as boards bigger then 10cm x 10cm manufacturing price is different. Most of the components are surface mounted on the top layer. No surface mounted components are placed on the bottom layer.

	=== Design power amplifier board===		=== Design power amplifier board===

@@ Line 44: / Line 44: @@
 === Design DAC board===
 The DAC board is the main PCB board (central board) that is connected to D class Power amplifier, GPS board, FPGA, User interface (LabVIEW) and power supply which power all these devices. The components used for the three phases and neutral are exactly the same to minimize the error that may contribute to the output signals.
 The schematic is designed to clearly illustrate each phase and neutral by minimizing the interconnection between the phases. However, the phase A and B using a dual op-amp for level shifting while each uses two other op-amps to provide a differential output to the power amplifier. Phase C and neutral connection use the same method.
 Housing the DACs, rail-to-rail operation amplifiers, Hex inverter at the input of the DAC.
 Power supply and voltage regulators are placed at the top of the PCB. The regulators are placed very close to the edge of the board because they require heatsinking. During normal operation the regulator is fine but when the load is connected, regulators tend to become hot.
 The output pins are placed on the right-hand side so as the power supply to the D Class power amplifier. Most of the header pins are placed on the left-hand side next to 40 pin header which is connected to FPGA.
 Hex inverter, DAC and Operational Amplifiers: all the interconnections.
 FPGA is connected to the DAC board by 40 pin header connection. Therefore, FPGA is controlled Through the DAC board.
 DAC board also house the power supply that power all the circuit (FPGA, DAC, op-amp and the power amplifier).
-The bypass capacitor is used at the positive terminals of the op-amp to short AC signal to the ground leaving cleaner DC voltage at the DC supply. It is essentially bypassing or filtering the AC noise present at the DC supply. This method ensures a cleaner signal output from the DAC board to the power amplifier board and transformer. Consequently, producing a clean sinusoidal waveform that has minimum THD.
+DAC board also house the power supply that power all the circuit (FPGA, DAC, op-amp and the power amplifier).
 Bypass capacitors are used at every DC power supply in order to minimize the noise and distortion that could contribute to the output signal.

← Older revision		Revision as of 06:29, 10 June 2019
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	=== Design DAC board===		=== Design DAC board===
		+	The DAC board is the main PCB board (central board) that is connected to D class Power amplifier, GPS board, FPGA, User interface (LabVIEW) and power supply which power all these devices. The components used for the three phases and neutral are exactly the same to minimize the error that may contribute to the output signals.
		+	The schematic is designed to clearly illustrate each phase and neutral by minimizing the interconnection between the phases. However, the phase A and B using a dual op-amp for level shifting while each uses two other op-amps to provide a differential output to the power amplifier. Phase C and neutral connection use the same method.
		+	Housing the DACs, rail-to-rail operation amplifiers, Hex inverter at the input of the DAC.
		+	Power supply and voltage regulators are placed at the top of the PCB. The regulators are placed very close to the edge of the board because they require heatsinking. During normal operation the regulator is fine but when the load is connected, regulators tend to become hot.
		+	The output pins are placed on the right-hand side so as the power supply to the D Class power amplifier. Most of the header pins are placed on the left-hand side next to 40 pin header which is connected to FPGA.
		+	Hex inverter, DAC and Operational Amplifiers: all the interconnections.
		+	FPGA is connected to the DAC board by 40 pin header connection. Therefore, FPGA is controlled Through the DAC board.
		+	DAC board also house the power supply that power all the circuit (FPGA, DAC, op-amp and the power amplifier).
		+	The bypass capacitor is used at the positive terminals of the op-amp to short AC signal to the ground leaving cleaner DC voltage at the DC supply. It is essentially bypassing or filtering the AC noise present at the DC supply. This method ensures a cleaner signal output from the DAC board to the power amplifier board and transformer. Consequently, producing a clean sinusoidal waveform that has minimum THD.
		+	Bypass capacitors are used at every DC power supply in order to minimize the noise and distortion that could contribute to the output signal.

	=== Design power amplifier board===		=== Design power amplifier board===