Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation - Revision history

A1701473: /* Averaging filter */

2020-06-09T02:29:57Z

‎Averaging filter

A1701473: /* Phase and magnitude module using LUT and interpolation method */

2020-06-09T02:27:53Z

‎Phase and magnitude module using LUT and interpolation method

A1701473: /* Phase and magnitude module using LUT and interpolation method */

2020-06-09T02:26:31Z

‎Phase and magnitude module using LUT and interpolation method

A1701473 at 02:23, 9 June 2020

2020-06-09T02:23:27Z

A1701473: /* Averaging filter */

2020-06-09T02:17:09Z

‎Averaging filter

A1701473 at 02:13, 9 June 2020

2020-06-09T02:13:33Z

A1701473 at 02:12, 9 June 2020

2020-06-09T02:12:39Z

A1757608: /* LabView Data Display */

2020-06-09T01:09:11Z

‎LabView Data Display

A1757608: /* LabView Data Display */

2020-06-09T01:07:17Z

‎LabView Data Display

A1757608: /* Results */

2020-06-09T01:06:49Z

‎Results

@@ Line 43: / Line 43: @@
 == Averaging filter ==
 [[File:Averaing filter.png|thumb]]
-In the block diagram of PMU, each phase will have two FIR filters to filter out the noise for both I and Q down-conversion.  For the three phase mains voltage, the system will need six FIR filters. In the IEEE Std C37.118.1-2011[1], it suggests to use a two-cycle triangular filter instead of a rectangular filter. Both triangular and averaging filters have a harmonic rejection to help the IIR filter to filter out the 2nd harmonic at 50Hz after the down-conversion. The advantage of triangular filters is that it has better side lobe attenuation than rectangular filters. However, each tap in the triangular filter is going to multiply with a coefficient while the coefficient in a rectangular filter is just 1 which does not need a multiplier in the calculation. The PMU design is using 10kHz sampling rate ADC and 50Hz mains voltage. It is equal to 200 samples per 50Hz cycle, which means it is going to take 200 taps for the averaging filter and 400 taps for a two-cycle triangular filter. Each triangular needs one multiplication and we need six of them to work for 3 phase voltage. The DE10-Lite FPGA board only has 144 18 by 18 multipliers which is not enough to implement them. Therefore, the 200 taps averaging filter will be a good choice for the DE10-Lite FPGA board. As shown in figure 5 drawn in Matlab, in the time domain from 0 to 200, for each tap the impulse response is 0.005. In terms of frequency domain, the greatest side lobe attenuation is -13.3 dB. The 2nd order harmonic rejection is at 0.01 fn. The 2nd harmonic in normalized frequency is 50/5000=0.01. Therefore the 2nd harmonic rejection attenuation is -33dB at 50Hz.
+In the block diagram of PMU, each phase will have two FIR filters to filter out the noise for both I and Q down-conversion.  For the three phase mains voltage, the system will need six FIR filters. We need to use a two-cycle triangular filter instead of a rectangular filter. Both triangular and averaging filters have a harmonic rejection to help the IIR filter to filter out the 2nd harmonic at 50Hz after the down-conversion. The advantage of triangular filters is that it has better side lobe attenuation than rectangular filters. However, each tap in the triangular filter is going to multiply with a coefficient while the coefficient in a rectangular filter is just 1 which does not need a multiplier in the calculation. The PMU design is using 10kHz sampling rate ADC and 50Hz mains voltage. It is equal to 200 samples per 50Hz cycle, which means it is going to take 200 taps for the averaging filter and 400 taps for a two-cycle triangular filter. Each triangular needs one multiplication and we need six of them to work for 3 phase voltage. The DE10-Lite FPGA board only has 144 18 by 18 multipliers which is not enough to implement them. Therefore, the 200 taps averaging filter will be a good choice for the DE10-Lite FPGA board. As shown in figure 5 drawn in Matlab, in the time domain from 0 to 200, for each tap the impulse response is 0.005. In terms of frequency domain, the greatest side lobe attenuation is -13.3 dB. The 2nd order harmonic rejection is at 0.01 fn. The 2nd harmonic in normalized frequency is 50/5000=0.01. Therefore the 2nd harmonic rejection attenuation is -33dB at 50Hz.
 == Phase and magnitude module using LUT and interpolation method ==

@@ Line 47: / Line 47: @@
 == Phase and magnitude module using LUT and interpolation method ==
 The look-up-table method generally uses a table to store all the outputs for each possible input. Then every time an input arrives, the LUT will look up the matching value in the table to produce the output. It is a really fast method for producing the result. However, the table can be extremely large if there are many possible inputs. Therefore, it usually needed to be combined with another method, for example the interpolation method, in order to reduce its size. The interpolation is an algorithm to calculate the point in-between two function points using a number of points near the insert point. Therefore, the LUT can be re-sized to have a smaller number of entities uniformly distributed over the whole range. After an input arrives, the LUT will find the closest entity value and using the entity’s value and offset distance to calculate the final output. The interpolation is an estimation which will introduce an error. The design of the phase module needs to ensure that the error is under the requirement.
 In order to calculate the phase and magnitude of the voltage, square root function and  functions are required. The phase module will use LUT with interpolation to generate the result of the functions. a=arctan(y/x) has two inputs, in which x is the real part and y is the imagery part from IQ demodulation and filtered by averaging filters. Two inputs are both floating point numbers after the conversion. Only the mantissa part will go into the LUT but it will still greatly increase the size of the LUT. Therefore, the design breaks apart  into two separate functions  and .  is equivalent to  so that it only needs the inverse function which only requires one input.
 The interpolation will be applied for all three functions. After the LUT looks up the most k bits of the input, it uses direct equations to simulate the shape of the function using the nearest tabulated values. Five entity values will be required at most to generate the result. The choices of the interpolation method analyzed in this thesis will be linear, second order, third order and fourth order polynomial interpolations. The equations that provided by Professor Kikkert are:
@@ Line 61: / Line 62: @@
 Cc=CI-Ac/7;
 Where AI, BI, CI, DI are the calculation of intermediate coefficients.
 == IIR Filter ==

@@ Line 46: / Line 46: @@
 == Phase and magnitude module using LUT and interpolation method ==
 In order to calculate the phase and magnitude of the voltage, square root function and  functions are required. The phase module will use LUT with interpolation to generate the result of the functions. a=arctan(y/x) has two inputs, in which x is the real part and y is the imagery part from IQ demodulation and filtered by averaging filters. Two inputs are both floating point numbers after the conversion. Only the mantissa part will go into the LUT but it will still greatly increase the size of the LUT. Therefore, the design breaks apart  into two separate functions  and .  is equivalent to  so that it only needs the inverse function which only requires one input.
 The interpolation will be applied for all three functions. After the LUT looks up the most k bits of the input, it uses direct equations to simulate the shape of the function using the nearest tabulated values. Five entity values will be required at most to generate the result. The choices of the interpolation method analyzed in this thesis will be linear, second order, third order and fourth order polynomial interpolations. The equations that provided by Professor Kikkert are:
-Linear: YI1=Y(3)+x*Ac	(14)
+Linear: YI1=Y(3)+x*Ac;
-Second order polynomial: YI2=Y(3)+x*Ac+x*x*Bc	(15)
+Second order polynomial: YI2=Y(3)+x*Ac+x*x*Bc;
-Third order polynomial: YI3=Y(3)+x*Ac+x*x*Bc+x*x*x*Cc	(16)
+Third order polynomial: YI3=Y(3)+x*Ac+x*x*Bc+x*x*x*Cc;
-Fourth order polynomial: YI4=Y(3)+x*Ac+x*x*Bc+x*x*x*Cc+x*x*x*x*Dc	(17)
+Fourth order polynomial: YI4=Y(3)+x*Ac+x*x*Bc+x*x*x*Cc+x*x*x*x*Dc;
 For the equations above, Y(3) is the nearest data point tabulated in the LUT. X has w-k bits to index the distance to the closest tabulated values, where w is the input length and k is the look up length for LUT. Multipliers are required in the calculations. The 1st order interpolation requires 1 multiplier if both x and Ac are less than 18 bits. If one of them exceeds 18 bits, 2 multipliers can be combined to achieve the multiplication. Considering the situation where all the numbers are less than 18 bits, the required 18 by 18 bits multipliers for 1st, 2nd, 3rd and 4th order are 1, 3, 5 and 7. Ac,Bc,Cc and Dc are the coefficients calculated using another 4 closest data points Y(1), Y(2), Y(4) and Y(5). As shown in figure 6. The equations to calculate these coefficients are:
-AI=(Y(4)-Y(2))/2
+AI=(Y(4)-Y(2))/2;
-BI=(Y(4)+Y(2))/2-Y(3)
+BI=(Y(4)+Y(2))/2-Y(3);
-CI=(Y(5)-Y(4)+Y(2)-Y(1))/14
+CI=(Y(5)-Y(4)+Y(2)-Y(1))/14;
-Ac=(AI-CI)*7/6
+Ac=(AI-CI)*7/6;
-Bc=BI
+Bc=BI;
-Cc=CI-Ac/7
+Cc=CI-Ac/7;
 Where AI, BI, CI, DI are the calculation of intermediate coefficients.
 == IIR Filter ==
 [[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

@@ Line 42: / Line 42: @@
 The digitised 16 bits input from the ADC is multiplied with quadrature signals generated from the LuT. The multiplication process utilises the 18-bit x 18-bit embedded multiplier inside the MAX10. Although there many multiplication algorithms that can be implemented such as Booth multiplication algorithms, using the embedded multiplier prove to be the easiest to implement. The embedded multipliers take account the signed integer during the multiplication process. There no need for an extra algorithm to sort the signed bits for the multiplication.
 == Averaging filter ==
 In the block diagram of PMU, each phase will have two FIR filters to filter out the noise for both I and Q down-conversion.  For the three phase mains voltage, the system will need six FIR filters. In the IEEE Std C37.118.1-2011[1], it suggests to use a two-cycle triangular filter instead of a rectangular filter. Both triangular and averaging filters have a harmonic rejection to help the IIR filter to filter out the 2nd harmonic at 50Hz after the down-conversion. The advantage of triangular filters is that it has better side lobe attenuation than rectangular filters. However, each tap in the triangular filter is going to multiply with a coefficient while the coefficient in a rectangular filter is just 1 which does not need a multiplier in the calculation. The PMU design is using 10kHz sampling rate ADC and 50Hz mains voltage. It is equal to 200 samples per 50Hz cycle, which means it is going to take 200 taps for the averaging filter and 400 taps for a two-cycle triangular filter. Each triangular needs one multiplication and we need six of them to work for 3 phase voltage. The DE10-Lite FPGA board only has 144 18 by 18 multipliers which is not enough to implement them. Therefore, the 200 taps averaging filter will be a good choice for the DE10-Lite FPGA board. As shown in figure 5 drawn in Matlab, in the time domain from 0 to 200, for each tap the impulse response is 0.005. In terms of frequency domain, the greatest side lobe attenuation is -13.3 dB. The 2nd order harmonic rejection is at 0.01 fn. The 2nd harmonic in normalized frequency is 50/5000=0.01. Therefore the 2nd harmonic rejection attenuation is -33dB at 50Hz.
 == IIR Filter ==
 [[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

@@ Line 42: / Line 42: @@
 The digitised 16 bits input from the ADC is multiplied with quadrature signals generated from the LuT. The multiplication process utilises the 18-bit x 18-bit embedded multiplier inside the MAX10. Although there many multiplication algorithms that can be implemented such as Booth multiplication algorithms, using the embedded multiplier prove to be the easiest to implement. The embedded multipliers take account the signed integer during the multiplication process. There no need for an extra algorithm to sort the signed bits for the multiplication.
 == Averaging filter ==
 In the block diagram of PMU, each phase will have two FIR filters to filter out the noise for both I and Q down-conversion.  For the three phase mains voltage, the system will need six FIR filters. In the IEEE Std C37.118.1-2011[1], it suggests to use a two-cycle triangular filter instead of a rectangular filter. Both triangular and averaging filters have a harmonic rejection to help the IIR filter to filter out the 2nd harmonic at 50Hz after the down-conversion. The advantage of triangular filters is that it has better side lobe attenuation than rectangular filters. However, each tap in the triangular filter is going to multiply with a coefficient while the coefficient in a rectangular filter is just 1 which does not need a multiplier in the calculation. The PMU design is using 10kHz sampling rate ADC and 50Hz mains voltage. It is equal to 200 samples per 50Hz cycle, which means it is going to take 200 taps for the averaging filter and 400 taps for a two-cycle triangular filter. Each triangular needs one multiplication and we need six of them to work for 3 phase voltage. The DE10-Lite FPGA board only has 144 18 by 18 multipliers which is not enough to implement them. Therefore, the 200 taps averaging filter will be a good choice for the DE10-Lite FPGA board. As shown in figure 5 drawn in Matlab, in the time domain from 0 to 200, for each tap the impulse response is 0.005. In terms of frequency domain, the greatest side lobe attenuation is -13.3 dB. The 2nd order harmonic rejection is at 0.01 fn. The 2nd harmonic in normalized frequency is 50/5000=0.01. Therefore the 2nd harmonic rejection attenuation is -33dB at 50Hz.
 == IIR Filter ==
 [[File:IIR block diagram.png|300px|thumb|right|Block diagram of a second order IIR filter]]

← Older revision		Revision as of 01:09, 9 June 2020
Line 140:		Line 140:

	== Results ==		== Results ==
−	~~=== LabView Data Display ===~~
−
−	~~<gallery>~~
−	~~Example.jpg\|Caption1~~
−	~~Example.jpg\|Caption2~~
−	~~</gallery>~~
−
	=== FLL Results ===		=== FLL Results ===

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 == Results ==
 === LabView Data Display ===
-[[File:LabView Interface.png|thumb]]
 === FLL Results ===

← Older revision		Revision as of 01:06, 9 June 2020
Line 140:		Line 140:

	== Results ==		== Results ==
		+	=== LabView Data Display ===
		+	[[File:LabView Interface.png\|thumb]]

	=== FLL Results ===		=== FLL Results ===