Projects:2020s1-1210 Performance Evaluation of Cryptographic Functions - Revision history

A1690722 at 05:34, 16 October 2020

2020-10-16T05:34:07Z

2020-10-16T05:30:21Z

2020-10-16T05:13:46Z

‎Performance Metrics

2020-10-16T05:13:24Z

‎Performance Metrics

2020-10-16T05:08:20Z

‎Implementation Platforms

2020-10-15T02:44:18Z

‎Conclusions

2020-10-15T02:43:39Z

‎Results

2020-10-15T02:41:53Z

‎Method

2020-10-15T02:38:45Z

‎Aims & Objectives

2020-10-15T02:38:31Z

‎Aims & Objectives

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 Results were collected using a range of different cipher modes from AES. Both accelerated implementations generally saw large performance increases compared to the software implementation, with hybrid outperforming hardware in most cases.
-A fascinating exception to this trend is when the GCM cipher mode is used. In this mode the hybrid implementation shows almost no improvement over software, however the hardware implementation completes the operation in 1/1000th of the time as it can execute the operation in parallel.
+A fascinating exception to this trend is when the GCM cipher mode is used. In this mode the hybrid implementation shows almost no improvement over software, however the hardware implementation completes the operation in 1/1000th of the time as it can execute the operation in parallel. GCM is likely to run faster on the software and hybrid implementations when a different algorithm for calculating the GHASH value required, however will not catch up to the hardware implementation speed greatly unless hardware acceleration for the calculation of the GHASH value is provided.
 [[File:GCM Implementation Results.JPG|thumb|Results from GCM mode showed a remarkable performance advantage favouring the Hardware Implementation]]

@@ Line 48: / Line 48: @@
 * The result of the hybrid implementation outperforming the hardware implementation is unexpected.
 * This is likely due to the hardware overhead running on the processor rather than an external memory controller.
-* The hybrid implementation is superior for small scale tasks, but the hardware implementation will outperform in tasks that are parallelized.
+* The hybrid implementation is superior for small scale tasks, but the hardware implementation will outperform in tasks that are parallelised.

@@ Line 34: / Line 34: @@
 == Results ==
 ===Performance Metrics===
 Results were collected using a range of different cipher modes from AES. Both accelerated implementations generally saw large performance increases compared to the software implementation, with hybrid outperforming hardware in most cases.
 A fascinating exception to this trend is when the GCM cipher mode is used. In this mode the hybrid implementation shows almost no improvement over software, however the hardware implementation completes the operation in 1/1000th of the time as it can execute the operation in parallel.

@@ Line 35: / Line 35: @@
 ===Performance Metrics===
 Results were collected using a range of different cipher modes from AES. Both accelerated implementations generally saw large performance increases compared to the software implementation, with hybrid outperforming hardware in most cases.
 A fascinating exception to this trend is when the GCM cipher mode is used. In this mode the hybrid implementation shows almost no improvement over software, however the hardware implementation completes the operation in 1/1000th of the time as it can execute the operation in parallel.
 ===Cost Metrics===

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 == Implementation Platforms ==
 All implementations of AES were tested on the RV32IC_P5, running on an Arty A7 100T FPGA Development Board.
 '''Software Implementation:''' The software implementation used the base RV32IC_P5 with no additional hardware acceleration.

← Older revision		Revision as of 02:44, 15 October 2020
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	== Conclusions ==		== Conclusions ==
		+	* The result of the hybrid implementation outperforming the hardware implementation is unexpected.
		+	* This is likely due to the hardware overhead running on the processor rather than an external memory controller.
		+	* The hybrid implementation is superior for small scale tasks, but the hardware implementation will outperform in tasks that are parallelized.

← Older revision		Revision as of 02:43, 15 October 2020
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	== Results ==		== Results ==
		+	===Performance Metrics===
		+	Results were collected using a range of different cipher modes from AES. Both accelerated implementations generally saw large performance increases compared to the software implementation, with hybrid outperforming hardware in most cases.

		+	A fascinating exception to this trend is when the GCM cipher mode is used. In this mode the hybrid implementation shows almost no improvement over software, however the hardware implementation completes the operation in 1/1000th of the time as it can execute the operation in parallel.
		+
		+	===Cost Metrics===
		+	It was also observed that the hardware implementation has the largest FPGA utilisation, with software being the smallest and hybrid the median. Conversely the hardware implementation has the smallest code size, with software being the largest, and hybrid again the median. Memory utilisation was relatively consistent between implementations.

	== Conclusions ==		== Conclusions ==

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 * Provide analysis regarding the relative performance of each implementation in terms of cost and performance.
-== Method ==
+== Implementation Platforms ==
 == Results ==

@@ Line 15: / Line 15: @@
 Encryption is a security measure that underpins private communication of data between devices on the internet. The Advanced Encryption Standard (AES) defines the algorithm used to encrypt data before it is sent. As a company developing processors for use in Internet of Things devices, the Australian Semiconductor Technology Company (ASTC) is interested in the performance of their designs when used for encryption tasks. To this end, ASTC have requested an investigation into processor performance when conducting encryption operations with varying degrees of hardware acceleration.
-=== Aims & Objectives ===
+== Aims & Objectives ==
 * Produce three different implementations of AES on ASTC’s RV32IC_P5 RISC_V processor with varying levels of hardware acceleration.
 * Provide analysis regarding the relative performance of each implementation in terms of cost and performance.