Projects:DELETE ME - Revision history

A1210973: Redirected page to Projects:2014S1-48 FPGA-based Software GPS Receiver

2014-10-14T00:46:08Z

Redirected page to Projects:2014S1-48 FPGA-based Software GPS Receiver

A1210973: A1210973 moved page Projects:2014S1-48 FPGA Based Software GPS Receiver to Projects:DELETE ME

2014-10-14T00:41:26Z

A1210973 moved page Projects:2014S1-48 FPGA Based Software GPS Receiver to Projects:DELETE ME

A1210973: Blanked the page

2014-10-14T00:41:04Z

Blanked the page

A1218706 at 04:54, 1 October 2014

2014-10-01T04:54:50Z

A1218706 at 04:53, 1 October 2014

2014-10-01T04:53:20Z

A1218706: Created page with "Project Summary: It is possible to run a GPS receiver completely in software, however due to the high data rate (1 MHz) of the incoming GPS codes it is very CPU intensive. GP..."

2014-10-01T04:52:08Z

Created page with "Project Summary: It is possible to run a GPS receiver completely in software, however due to the high data rate (1 MHz) of the incoming GPS codes it is very CPU intensive. GP..."

New page

Project Summary:

It is possible to run a GPS receiver completely in software, however due to the high data rate (1 MHz) of the incoming GPS codes it is very CPU intensive. GPS receivers have traditionally solved this problem by using custom chips as co-processors to a more traditional CPU. These custom chips handle the high-bandwith, low bit resolution data processing, allowing the CPU to handle the lower data rate algorithm for determing the position solution. FPGA devices can be programmed to replace the custom chips. Furthermore, a soft-core CPU can be programmed onto the FPGA fabric to implement the
algorithm that typically resides on a CPU in a traditional GPS receiver. In this way the complete GPS receiver can be implemented on a single FPGA. More recent FPGA chips include a hard-core CPU to implement a comlete system-on- a-chip (SOC), see http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/
The aim of this project is to implement a GPS receiver on such a SOC. The project will be based on an existing GPS receiver implementation possibly the one available from: http://www.aholme.co.uk/GPS/Main.htm which uses an FPGA together with a raspberry pie processor. The main task would be to port the C code from the raspberry pie onto the procesor inside the FPGA. The project also requires a GPS RF front end to be interfaces to the FPGA to receiver the GPS signals from an antenna.

== '''Team members'''==

Patrick Mead
WEI LIU
Victor Yuan

== '''Project Supervisors'''==
Matthew Trinkle
Braden Phillips

← Older revision	Revision as of 00:46, 14 October 2014
Line 1:	Line 1:
−	+	#REDIRECT [[Projects:2014S1-48 FPGA-based Software GPS Receiver]]

← Older revision		Revision as of 00:41, 14 October 2014
Line 1:		Line 1:

−	~~== '''Project Summary''' ==~~
−
−
−	It is possible to run a GPS receiver completely in software, however due to the high data rate (1 MHz) of the incoming GPS codes it is very CPU intensive. GPS receivers have traditionally solved this problem by using custom chips as co-processors to a more traditional CPU. These custom chips handle the high-bandwith, low bit resolution data processing, allowing the CPU to handle the lower data rate algorithm for determing the position solution. FPGA devices can be programmed to replace the custom chips. Furthermore, a soft-core CPU can be programmed onto the FPGA fabric to implement the
−	algorithm that typically resides on a CPU in a traditional GPS receiver. In this way the complete GPS receiver can be implemented on a single FPGA. More recent FPGA chips include a hard-core CPU to implement a comlete system-on- a-chip (SOC), see http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/
−	The aim of this project is to implement a GPS receiver on such a SOC. The project will be based on an existing GPS receiver implementation possibly the one available from: http://www.aholme.co.uk/GPS/Main.htm which uses an FPGA together with a raspberry pie processor. The main task would be to port the C code from the raspberry pie onto the procesor inside the FPGA. The project also requires a GPS RF front end to be interfaces to the FPGA to receiver the GPS signals from an antenna.
−
−
−
−	~~== '''Team members'''==~~
−
−	~~Patrick Mead;~~
−	~~WEI LIU;~~
−	~~Victor Yuan~~
−
−
−	~~== '''Project Supervisors'''==~~
−	~~Matthew Trinkle;~~
−	~~Braden Phillips~~

← Older revision		Revision as of 04:53, 1 October 2014
Line 1:		Line 1:
−	Project Summary:	+
		+	== '''Project Summary''' ==
		+

	It is possible to run a GPS receiver completely in software, however due to the high data rate (1 MHz) of the incoming GPS codes it is very CPU intensive. GPS receivers have traditionally solved this problem by using custom chips as co-processors to a more traditional CPU. These custom chips handle the high-bandwith, low bit resolution data processing, allowing the CPU to handle the lower data rate algorithm for determing the position solution. FPGA devices can be programmed to replace the custom chips. Furthermore, a soft-core CPU can be programmed onto the FPGA fabric to implement the		It is possible to run a GPS receiver completely in software, however due to the high data rate (1 MHz) of the incoming GPS codes it is very CPU intensive. GPS receivers have traditionally solved this problem by using custom chips as co-processors to a more traditional CPU. These custom chips handle the high-bandwith, low bit resolution data processing, allowing the CPU to handle the lower data rate algorithm for determing the position solution. FPGA devices can be programmed to replace the custom chips. Furthermore, a soft-core CPU can be programmed onto the FPGA fabric to implement the

← Older revision	Revision as of 00:41, 14 October 2014
(No difference)

@@ Line 11: / Line 11: @@
 == '''Team members'''==
-Patrick Mead
+Patrick Mead;
-WEI LIU
+WEI LIU;
 Victor Yuan
 == '''Project Supervisors'''==
-Matthew Trinkle
+Matthew Trinkle;
 Braden Phillips