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| − | == '''Project Summary''' ==
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| − | It is possible to run a GPS receiver completely in software, however due to the high data rate (1 MHz) of the incoming GPS codes it is very CPU intensive. GPS receivers have traditionally solved this problem by using custom chips as co-processors to a more traditional CPU. These custom chips handle the high-bandwith, low bit resolution data processing, allowing the CPU to handle the lower data rate algorithm for determing the position solution. FPGA devices can be programmed to replace the custom chips. Furthermore, a soft-core CPU can be programmed onto the FPGA fabric to implement the
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| − | algorithm that typically resides on a CPU in a traditional GPS receiver. In this way the complete GPS receiver can be implemented on a single FPGA. More recent FPGA chips include a hard-core CPU to implement a comlete system-on- a-chip (SOC), see http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/
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| − | The aim of this project is to implement a GPS receiver on such a SOC. The project will be based on an existing GPS receiver implementation possibly the one available from: http://www.aholme.co.uk/GPS/Main.htm which uses an FPGA together with a raspberry pie processor. The main task would be to port the C code from the raspberry pie onto the procesor inside the FPGA. The project also requires a GPS RF front end to be interfaces to the FPGA to receiver the GPS signals from an antenna.
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| − | == '''Team members'''==
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| − | Patrick Mead;
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| − | WEI LIU;
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| − | Victor Yuan
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| − | == '''Project Supervisors'''==
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| − | Matthew Trinkle;
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| − | Braden Phillips
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