Difference between revisions of "Projects:2019s2-25601 Phasor Measurement Unit: FPGA Implementation"
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* Rui Yang | * Rui Yang | ||
* Mohamad Hafiz Mohamad Rodzi | * Mohamad Hafiz Mohamad Rodzi | ||
| − | * | + | * JunWen Zheng |
| − | * Sayed Mohd Amir Shahirudin Sayed Sagar | + | * Sayed Mohd Amir Shahirudin Sayed Sagar |
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==== Supervisors ==== | ==== Supervisors ==== | ||
* A/Prof. Cornelis Keith Kikkert | * A/Prof. Cornelis Keith Kikkert | ||
Revision as of 20:09, 7 June 2020
Phasor Measurement Unit(PMU) is essential in the power industry in order to maintain the stability of the power network. Thus a need for a PMU that has a very high precision is a must. This project will try to implement a Matlab algorithm that was created by Prof C.J Kikkert into FPGA
Contents
Introduction
Project description here
Project team
Project students
- Rui Yang
- Mohamad Hafiz Mohamad Rodzi
- JunWen Zheng
- Sayed Mohd Amir Shahirudin Sayed Sagar
Supervisors
- A/Prof. Cornelis Keith Kikkert
- Said Al-Sarawi
Advisors
Objectives
Set of objectives To Implement floating-point algorithm as fixed-point algorithm in FPGA
Background
IIR Filter
This topic presents the development of the IIR filter towards the implementation of FPGA. The algorithm of the filter is designed by Adjunct A/Prof. C.J. Kikkert in MATLAB that suited to implementation in an FPGA. The paper wrote by him proves that the filter utilise fewer resources compared to the reference Finite Impulse Response (FIR) in the IEC/IEEE standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power systems. This section shows the VHDL routines designed in the Quartus Prime software based on the MATLAB algorithm. VHDL is a hardware description language used to program the FPGA board. The IIR filter will make use of the IEEE 754 floating-point standard. The operations are carried on mantissa, exponents, and sign components. This includes the routine to convert the filter coefficients from the algorithms in a signed floating-point format.
Literature Review
Agarwal, Verma, Tiwari et al. [6] only used the anti-aliasing filter in their PMU design. Ref [7] designing a virtual PMU to interact with the real-time simulators as a way emulating the large number of real-life PMUs. They used the anti-aliasing filter to filter out the voltage and current analog inputs before the computation begins. Ref [8] reports that their PMU design is using the window method of FIR filter. The performance of the filter is investigated based on out of band rejection, noise, and harmonic elimination. The sixth order IIR filter in this project satisfies all the IEC/IEEE standard limit at 48 Hz main frequency
Method
Results
Conclusion
References
[1] a, b, c, "Simple page", In Proceedings of the Conference of Simpleness, 2010.
