Projects:2018s2-235UG PMU Test generator

From Projects
Revision as of 17:04, 10 June 2019 by A1680764 (talk | contribs) (→‎Design power amplifier board)
Jump to: navigation, search

Introduction

A PMU test generator is a calibration equipment that test PMU under different condition per IEEE C37.118.1.2011 and IEEE C37.118.1.2014 standards requirements by applying three phase signal with exact 120 degrees phase shift to the system and measure its response The response is to be compared with the generated signal.

Motivation

In the global power system, the operation is often close to its stability limit, which means that any disturbance or fault may lead to power oscillation and cascade power outages. The motivation for this project is to use the PMU test generator for real-time monitoring to make power distribution more stable and secure and even to transition to renewable energy sources. Of course, under the leadership of Dr. Keith Kikkert, we will make a cheaper version of the model and reduce the cost of the model accordingly.

Objectives

This project aims to build a three-phase PMU test generator that can generate all the test signals mentioned in IEEE C37.118.1 (2011 and 2014). The instrument will generate waveforms digitally and convert them to analog waveforms using a digital-to-analog converter and up to the 1W audio amplifier. The generator will generate a three-phase signal of 50 Hz.

  • 1) Real state:

In a stable state, people can change the frequency to 5Hz, and the amplitude can also change to 20% by adjusting the instrument. It can also modulate frequency slopes, amplitudes and frequency wavelengths, and AM and FM modulation of three-phase signals at a rate of 0.1-2HZ. The waveform of the 3 phase is easy to distort.

  • 2) Ideal state:

In ideally, the instrument would be controlled by a computer's LabView or hardware binary to complete all IEEE C37.118.1 (2011 and 2014). In order to achieve precise timing, digital waveforms can be generated by using the FPGA development board, and PCB boards that can accommodate amplifiers and DACs. Transformers also produce 230V waveforms.

Project Team

project student :

  • Yasin Mohammadi
  • George Qian

supervisors :

  • Prof. Keith Kikkert
  • Prof. Nesimi Ertugrul

Background

Phasor measurement Unit

PMU is a device used to estimate the amplitude and phase angle of phasor in power grid by using synchronous common time source. Nowadays, it is more used to detect whether the smart grid is stable. About the history of PMU, in 1893, Charles Proteus Steinmetz published a paper on clear mathematical descriptions of AC waveforms, which he called phasors, a small point of PMU for the first time. The phasor measurement unit (PMU), which was invented by Dr. Arun G. Phadke and Dr. James S. Thorp at Virginia Tech in 1988, was an early model of PMU, and Macrodyne built the first real PMU in 1992 [3]. Since the 1990s, PMU has been installed in power grids in North America and many other countries in the world. The field test of synchronous phasor measurement technology not only verifies the effectiveness of simultaneous phasor measurement but also accumulates experience for the field operation of PMU [3]. Synchronous phasor measurements will allow people to measure and analyze the state of the entire power system more accurately based on real-time data collected from phasor measurement units located throughout the network. Accurate and time-labeled phasor data can be collected promptly, which allows system controllers to quickly identify power system events, such as power flow problems, frequency variability from different parts of the system and dynamic angle separation problems, through visual systems. The monitoring provides an accurate method for controlling the power flow from multiple energy sources (nuclear, coal, wind). PMU provides utilities with more control and monitoring capabilities and is considered one of the most basic measurement devices in future power systems. PMU can reduce load and other load control technology, honestly realize the management of power system and improve the reliability of power grid by early detection of faults, to achieve the isolation of operating system, to prevent blackouts. Accurate analysis and automatic correction of system degradation source to improve power quality. These are the original intentions of this project [3].

Design

Project process

The project process of PMU

Project design uses regularity extensively throughout process by designing and simulating phase A only and apply the same design to phase B and C.

Approach

The approach of PMU test generator

The design, development and testing of PMU test generator follows system engineering approach using V model The V model process illustrate different stages of the conceptual exploration of the project verification process, implementation and validation of the system

Design DAC board

The DAC board is the main PCB board (central board) that is connected to D class Power amplifier, GPS board, FPGA, User interface (LabVIEW) and power supply which power all these devices. The components used for the three phases and neutral are exactly the same to minimize the error that may contribute to the output signals.

The schematic is designed to clearly illustrate each phase and neutral by minimizing the interconnection between the phases. However, the phase A and B using a dual op-amp for level shifting while each uses two other op-amps to provide a differential output to the power amplifier. Phase C and neutral connection use the same method.

Housing the DACs, rail-to-rail operation amplifiers, Hex inverter at the input of the DAC.

Power supply and voltage regulators are placed at the top of the PCB. The regulators are placed very close to the edge of the board because they require heatsinking. During normal operation the regulator is fine but when the load is connected, regulators tend to become hot.

The output pins are placed on the right-hand side so as the power supply to the D Class power amplifier. Most of the header pins are placed on the left-hand side next to 40 pin header which is connected to FPGA.

Hex inverter, DAC and Operational Amplifiers: all the interconnections.

FPGA is connected to the DAC board by 40 pin header connection. Therefore, FPGA is controlled Through the DAC board.

DAC board also house the power supply that power all the circuit (FPGA, DAC, op-amp and the power amplifier).

The bypass capacitor is used at the positive terminals of the op-amp to short AC signal to the ground leaving cleaner DC voltage at the DC supply. It is essentially bypassing or filtering the AC noise present at the DC supply. This method ensures a cleaner signal output from the DAC board to the power amplifier board and transformer. Consequently, producing a clean sinusoidal waveform that has minimum THD.

Bypass capacitors are used at every DC power supply in order to minimize the noise and distortion that could contribute to the output signal.

PCB is designed to house the voltage regulators at the edge (top) of the PCB in order to enable the heatsinking.

The input headers are placed at the left-hand side of the board near the 40pin header connected to the FPGA while the outputs are placed at the right-hand side that can be placed next to the power amplifier board.

Additionally, the jumper is placed at the output of each DAC that can be used to test the analog section of the project independent of the digital signal.

Double layer PCB is used to enable a compact design that uses fewer spaces and reduces the manufacturing prices as boards bigger then 10cm x 10cm manufacturing price is different. Most of the components are surface mounted on the top layer. No surface mounted components are placed on the bottom layer.

Design power amplifier board

Power amplifier Schematic and PCB layout are in accordance with the recommended Schematic and PCB in TPA3244 datasheet [9, p.22, p.38].

PCB has copper traces on both sides and they are showing as lines connecting terminals. As illustrated on the PCB layout, the input (left-hand side) and the output (right-hand side) of the power amplifier copper traces have different width.

The supply voltage decoupling capacitor is positioned close to the device per datasheet recommendation [9, Fig.23] connected directly to the device pin on the top layer. The decoupling capacitors values are also changed to 1000uF.

Power pads placed under devices for dissipating heat generated during operation.

Three LEDs placed on the board to indicate the state of the power amplifier. One of the LED is used to indicate the DC voltage presence to the board while the other two LEDs are used for error notification to the operation. at the input to enable visual inspection of the fault, over temperature and reset. During operation, all the LEDs are expected to be on indicating a healthy operation. As soon as one these turn off, The common one that might turn off is the fault that causes the power amplifier.

Testing

Conclusion

The project has now succeeded in achieving most of its objectives Each part of the hardware has been tested and is working correctly. The group has been successful in achieving output of 276 V without saturation and THD of less than 1%. For the future of this project, it should be the more advanced intelligent technology in the world today. Its appearance is crucial for the dynamic network. In the future, it may involve more fields and solve more complicated problems in human life

References

Retrieved from "https://projectswiki.eleceng.adelaide.edu.au/projects/index.php?title=Projects:2018s2-235UG_PMU_Test_generator&oldid=12713"