Projects:2017s1-135 A Low Cost Impedance Analyser

Abstract

This project has commenced in order to develop a low cost impedance analyser that can be used to perform measurements in a laboratory environment. The project will be able to significantly cut costs by utilising instruments and software already available from the University. The impedance analyser will make use of the voltage divider principle, where the impedance of a device under test (DUT) can be found by using the voltage divider equation. A signal generator will feed a signal into the main circuit and a digital oscilloscope will measure the resultant voltage output of the DUT. A resistor is placed in series with the DUT, where impedance matching will allow for higher accuracy results. Thus, a control mechanism circuit will also be developed to complement the main circuit.

The control mechanism circuit is comprised of a network of parallel resistors, where there are switches in each branch. The values of these resistors are per decade, from a minimum of 0.1 up to a maximum of 1 M. An FPGA will be able to determine which of the resistors has the closest value to the magnitude of the DUT’s impedance. The FPGA will then cause the switch to be closed, whilst leaving all other switches open. As a result, that resistor will then be in series with the DUT, completing the voltage divider circuit. This control mechanism is essentially behaving as an impedance matching circuit. A LabView program running on a PC will be developed that will communicate and control the developed impedance analyser. The signal generator, oscilloscope and impedance analyser will be connected to the PC via the USB protocol.

Preliminary results show that the analyser is able to acquire measurement data and hence it should be able to find the impedance of the DUT. The analyser should also able to find the transfer function characteristics of a filter. The obtained values will be compared against known impedances that have been calibrated with the analyser. The impedance analyser should be able to accurately determine the value of the known DUT, with a 0.1% accuracy tolerance.

Project Team

Student Members

• Muhamad Shaabuddin:

Bachelor of Engineering (Honours)(Electrical and Electronic) with Computer Science

• Filip Karisik:

Bachelor of Engineering (Honours)(Electrical and Electronic) with Finance

Academic Supervisors

• Dr Keith Kikkert

• Dr Dr Cheng-Chew Lim